Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
26 - Asynchronous sequential circuits
from Part VII - Asynchronous logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
Asynchronous sequential circuits have state that is not synchronized with a clock. Like the synchronous sequential circuits we have studied up to this point, they are realized by adding state feedback to combinational logic that implements a next-state function. Unlike synchronous circuits, the state variables of an asynchronous sequential circuit may change at any point in time. This asynchronous state update – from next state to current state – complicates the design process. We must be concerned with hazards in the next-state function, since a momentary glitch may result in an incorrect final state. We must also be concerned with races between state variables on transitions between states whose encodings differ in more than one variable.
In this chapter we look at the fundamentals of asynchronous sequential circuits. We start by showing how to analyze combinational logic with feedback by drawing a flow table. The flow table shows us which states are stable, which are transient, and which are oscillatory.We then show how to synthesize an asynchronous circuit from a specification by first writing a flow table and then reducing the flow table to logic equations. We see that state assignment is quite critical for asynchronous sequential machines, since it determines when a potential race may occur. We show that some races can be eliminated by introducing transient states.
After the introduction given in this chapter, we continue our discussion of asynchronous circuits in Chapter 27 by looking at latches and flip-flops as examples of asynchronous circuits.
FLOW-TABLE ANALYSIS
Recall from Section 14.1 that an asynchronous sequential circuit is formed when a feedback path is placed around combinational logic, as shown in Figure 26.1(a). To analyze such circuits, we break the feedback path as shown in Figure 26.1(b) and write the equations for the next-state variables as a function of the current-state variables and the inputs. We can then reason about the dynamics of the circuit by exploring what happens when the current-state variables are updated (in arbitrary order if multiple bits change) with their new values.
Information
- Type
- Chapter
- Information
- Digital Design Using VHDLA Systems Approach, pp. 551 - 565Publisher: Cambridge University PressPrint publication year: 2015
Accessibility standard: Unknown
Why this information is here
This section outlines the accessibility features of this content - including support for screen readers, full keyboard navigation and high-contrast display options. This may not be relevant for you.Accessibility Information
Accessibility compliance for the PDF of this chapter is currently unknown
and may be updated in the future.