Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
16 - Datapath sequential logic
from Part IV - Synchronous sequential logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
In Chapter 14 we saw how a finite-state machine can be synthesized from a state diagram by writing down a table for the next-state function and synthesizing the logic that realizes this table. For many sequential functions, however, the next-state function can be more simply described by an expression rather than by a table. Such functions are more efficiently described and realized as datapaths, where the next state is computed as a logical function, often involving arithmetic circuits, multiplexers, and other building block circuits.
COUNTERS
A simpler counter
Suppose you want to build a finite-state machine with the state diagram shown in Figure 16.1. This circuit is forced to state 0 whenever input r is true. Whenever input r is false, the machine counts through the states from 0 to 31 and then cycles back to 0. Because of this counting behavior, we refer to this finite-state machine as a counter.
We could design the counter employing the methodology developed in Chapter 14. A VHDL description taking this approach for a three-bit counter (eight states) is shown in Figure 16.2. A three-bit wide bank of flip-flops holds the current state, count, and updates it from the next state, nxt, on each rising edge of the clock. The matching case statement captures the state table, specifying the next state for each input and current state combination.
While this method for generating counters works, it is verbose and inefficient. The lines of the state table are repetitive. The behavior of the machine can be captured entirely by the single line
nxt ≤ (others => ’0’) when rst else count+1;
We use array aggregate notation, “(others => ’0’)”, to specify a std_logic_vector value with all elements equal to ’0’. This is a datapath description of the finite-state machine in which we specify the next state as a function of the current state and inputs.
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- Digital Design Using VHDLA Systems Approach, pp. 344 - 374Publisher: Cambridge University PressPrint publication year: 2015
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