Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- 20 Verification and test
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
20 - Verification and test
from Part V - Practical design
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- 20 Verification and test
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
Verification and test are engineering processes that complement design. Verification is the task of ensuring that a design meets its specification. On a typical digital systems project, more effort is expended on verification than on the design itself. Because of the high cost and long delays involved in fabricating a chip, thorough verification is essential to ensure that the chip works the first time. A design error that is not caught during verification would result in costly delays and retooling.
Testing is performed to ensure that a particular instantiation of a design functions properly. When a chip is fabricated, some transistors, wires, or contacts may be faulty. A manufacturing test is performed to detect these faults so the device can be repaired or discarded.
DESIGN VERIFICATION
Simulation is the primary tool used to verify that a design meets its specification. The design is simulated using a number of tests that provide stimulus to the unit being tested and check that the design produces correct outputs. The VHDL testbenches we have seen throughout this book are examples of such tests.
Verification coverage
The verification challenge amounts to ensuring that the set of test patterns, the test suite, written to verify a design is complete. We measure the degree of completion of a test suite by its coverage of the specification and of the implementation. We typically insist on 100% coverage of both specification features and implementation lines or edges to consider the design verified.
The specification coverage of a set of tests is measured by determining the fraction of features in the specification that are exercised and checked by the tests. For example, suppose you have developed a digital clock chip that includes a day/date and an alarm function. Table 20.1 gives a partial list of features to be tested. Even for something as simple as a digital clock, the list of features can easily run into the hundreds. For a complex chip it is not unusual to have 105 or more features. Each test verifies one or more features. As tests are written, the features covered by each test are checked off.
Information
- Type
- Chapter
- Information
- Digital Design Using VHDLA Systems Approach, pp. 453 - 464Publisher: Cambridge University PressPrint publication year: 2015
Accessibility standard: Unknown
Why this information is here
This section outlines the accessibility features of this content - including support for screen readers, full keyboard navigation and high-contrast display options. This may not be relevant for you.Accessibility Information
Accessibility compliance for the PDF of this chapter is currently unknown
and may be updated in the future.