High-Current Electrostatic Discharge Behavior

Charvaka Duvvury; Harald Gossner; Mayank Shrivastava

doi:10.1017/9781316105375.006

5 - High-Current Electrostatic Discharge Behavior

Published online by Cambridge University Press: 18 July 2026

Charvaka Duvvury ,

Harald Gossner and

Mayank Shrivastava

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Charvaka Duvvury: Affiliation:
iT2 Technologies
Harald Gossner: Affiliation:
Intel
Mayank Shrivastava: Affiliation:
Indian Institute of Science, Bangalore

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Summary

This chapter delves into the high-current behavior of semiconductor devices during electrostatic discharge events, focusing on the physical mechanisms leading to device failure. It outlines how ESD-induced phenomena such as dielectric breakdown, thermal runaway, and current filamentation differ from normal device operation. Detailed analysis is provided for various failure modes – voltage and current driven – and the associated temperature dynamics under transient stress. The chapter also explores device-specific responses, including NMOS snapback, bipolar triggering, and diode overshoot under ultra-fast pulses. High-current behavior of resistors, diodes, and transistors in advanced technologies, especially Fin-type Field Effect Transistor (FinFETs), is examined using both experimental and technology computer-aided design (TCAD) simulation data. The role of scaling in reducing device robustness and the importance of understanding electrothermal effects for ESD protection design are emphasized. This foundational understanding enables more accurate prediction of device limits and informs the design of robust, technology-scalable ESD protection solutions.

Keywords

Electrostatic Discharge (ESD)High-Current Behavior Dielectric Breakdown Thermal Runaway Snapback Filamentation n-Type Metal Oxide Semiconductor (NMOS)Diodes Avalanche Multiplication Technology Computer Aided Design (TCAD) Simulation Fin-type Field Effect Transistor (FinFET)Charge Modulation Self-Heating ESD Failure Mechanisms.

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Type: Chapter
Information: High Current ESD
Physics and Design
, pp. 119 - 224

DOI: https://doi.org/10.1017/9781316105375.006 [Opens in a new window]

Publisher: Cambridge University Press

Print publication year: 2026

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References

[1] Alvarez, D., Chatty, K., Russ, C., Abou-Khalil, M. J., Li, J., Gauthier, R., Esmark, K., Halbach, R., and Seguin, C.. Design optimization of gate-silicided ESD NMOSFETS in a 45nm bulk CMOS technology. In 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pages 1A.4-1–1A.4-9, 2007.CrossRef Google Scholar

[2] Appels, J. A. and Vaes, H. M. J.. High voltage thin layer devices (resurf devices). In 1979 International Electron Devices Meeting, pages 238–241. IEEE, 1979.Google Scholar

[3] Amerasekera, A. and Duvvury, C.. The impact of technology scaling on ESD robustness and protection circuit design. IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A, 18(2):314–320, 1995.Google Scholar

[4] Amerasekera, A., McNeil, V., and Rodder, M.. Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25/spl mu/m CMOS process. In International Electron Devices Meeting. Technical Digest, pages 893–896. IEEE, 1996.CrossRef Google Scholar

[5] Ajith Amerasekera, E. and Duvvury, C.. ESD in silicon integrated circuits. 2002.Google Scholar

[6] Bock, K., Keppens, B., De Heyn, V., Groeseneken, G., Ching, L.Y., and Naem, A.. Influence of gate length on ESD-performance for deep sub micron CMOS technology. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), pages 95–104, 1999.Google Scholar

[7] Boselli, G., Meeuwsen, S., Mouthaan, T., and Kuper, F.. Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), pages 11–18, 1999.Google Scholar

[8] Boselli, G., Vassilev, V., and Duvvury, C.. Drain extended NMOS high current behavior and ESD protection strategy for HV applications in sub-100 nm CMOS technologies. In 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, pages 342–347, 2007.CrossRef Google Scholar

[9] Breil, N., Lavoie, C., Ozcan, A., Baumann, F., Klymko, N., Nummy, K., Sun, B., Jordan-Sweet, J., Yu, J., Zhu, F., Narasimha, S., and Chudzik, M.. Challenges of nickel silicidation in CMOS technologies. Microelectronic Engineering, 137:79–87, 2015. Materials for Advanced Metallization 2014.CrossRef Google Scholar

[10] Caillard, B., Azais, F., Dournelle, S., Salome, P., and Nouet, P.. STMSCR: A new multi-finger SCR-based protection structure against ESD. In 2003 Electrical Overstress/Electrostatic Discharge Symposium, pages 1–9, 2003.Google Scholar

[11] Chatterjee, A., Shrivastava, M., Gossner, H., Pendharkar, S., Brewer, F., and Duvvury, C.. An insight into the ESD behavior of the nanometer-scale drain-extended NMOS device – Part I: Turn-on behavior of the parasitic bipolar. IEEE Transactions on Electron Devices, 58(2):309–317, 2011.Google Scholar

[12] Chatterjee, A., Shrivastava, M., Gossner, H., Pendharkar, S., Brewer, F., and Duvvury, C.. An insight into ESD behavior of nanometer-scale drain extended NMOS (DeNMOS) devices: Part II (two-dimensional study-biasing & comparison with NMOS). IEEE Transactions on Electron Devices, 58(2):318–326, 2011.Google Scholar

[13] Chan, V., Rim, K., Ieong, M., Yang, S., Malik, R., Teh, Y. W., Yang, M., and Qiqing. Strain for CMOS performance improvement. In Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005, pages 667–674, 2005.Google Scholar

[14] Chen, W.-Y., Ker, M.-D., Jou, Y.-N., Huang, Y.-J., and Lin, G.-L.. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICS by body current injection. In 2009 IEEE International Symposium on Circuits and Systems, pages 385–388, 2009.CrossRef Google Scholar

[15] Chen, W.-Y. and Ker, M.-D.. High-voltage NLDMOS in waffle-layout style with body-injected technique for ESD protection. IEEE Electron Device Letters, 30(4):389–391, 2009.Google Scholar

[16] Chen, T.-Y. and Ker, M.-D.. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices. IEEE Transactions on Device and Materials Reliability, 1(4):190–203, 2001.Google Scholar

[17] Chen, H.-W., Chen, S.-L., Huang, Y.-T., and Chen, H.-H.. ESD improvements on power n-channel LDMOS devices by the composite structure of super junctions integrated with SCRS in the drain side. IEEE Journal of the Electron Devices Society, 8:864–872, 2020.CrossRef Google Scholar

[18] Chung, Y. S. and Baird, B.. Electrical-thermal coupling mechanism on operating limit of LDMOS transistor. In International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), pages 83–86, 2000.CrossRef Google Scholar

[19] Colvin, J.. The identification and analysis of latent ESD damage on CMOS input gates. Journal of Electrostatics, 33(3):291–311, 1994.CrossRef Google Scholar

[20] Delage, C., Nolhier, N., Bafleur, M., Dorkel, J.-M., Hamid, H., Givelin, P., and Lin-Kwang, J.. The mirrored lateral SCR (MILSCR) as an ESD protection structure: Design and optimization using 2-D device simulation. IEEE Journal of Solid-State Circuits, 34(9):1283–1289, 1999.CrossRef Google Scholar

[21] Denison, M., Blaho, M., Silber, D., Joos, J., Jensen, N., Stecher, M., Dubec, V., Pogany, D., and Gornik, E.. Hot spot dynamics in quasivertical DMOS under ESD stress. In ISPSD ’03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings, pages 80–83, 2003.Google Scholar

[22] Denison, M., Blaho, M., Rodin, P., Dubec, V., Pogany, D., Silber, D., Gornik, E., and Stecher, M.. Moving current filaments in integrated DMOS transistors under short-duration current stress. IEEE Transactions on Electron Devices, 51(10):1695–1703, 2004.CrossRef Google Scholar

[23] Di Sarro, J., Chatty, K., Gauthier, R., and Rosenbaum, E.. Study of design factors affecting turn-on time of silicon controlled rectifiers (SCRS) in 90 and 65 nm bulk CMOS technologies. In 2006 IEEE International Reliability Physics Symposium Proceedings, pages 163–168, 2006.CrossRef Google Scholar

[24] Duvvury, C., Rodriguez, J., Jones, C., and Smayling, M.. Device integration for ESD robustness of high voltage power mosfets. In Proceedings of 1994 IEEE International Electron Devices Meeting, pages 407–410, 1994.CrossRef Google Scholar

[25] Duvvury, C., Carvajal, F., Jones, C., and Briggs, D.. Lateral DMOS design for ESD robustness. In International Electron Devices Meeting. IEDM Technical Digest, pages 375–378, 1997.CrossRef Google Scholar

[26] Dwyer, V. M., Franklin, A. J., and Campbell, D. S.. Thermal failure in semiconductor devices. Solid-State Electronics, 33(5):553–560, 1990.CrossRef Google Scholar

[27] Dwyer, V. M., Franklin, A. J., and Campbell, D. S.. Electrostatic discharge thermal failure in semiconductor devices. IEEE Transactions on Electron Devices, 37(11):2381–2387, 1990.CrossRef Google Scholar

[28] Erlbacher, T.. Lateral Power Transistors in Integrated Circuits. Springer, January 2014.CrossRef Google Scholar

[29] Gossner, H., Esmark, K., and Stadler, W.. Simulation Methods for ESD Protection Development. Elsevier, Oct 2003.Google Scholar

[30] Furbock, C., Pogany, D., Litzenberger, M., Gornik, E., Seliger, N., Gossner, H., Muller-Lynch, T., Stecher, M., and Werner, W.. Interferometric temperature mapping during ESD stress and failure analysis of smart power technology ESD protection devices. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), pages 241–250, 1999.Google Scholar

[31] Goldstein, M., Sölkner, G., and Gornik, E.. Heterodyn interferometer for the detection of electric and thermal signals in integrated circuits through the substrate. Review of Scientific Instruments, 64(10):3009–3013, 10 1993.CrossRef Google Scholar

[32] Gossner, H., Muller-Lynch, T., Esmark, K., and Stecher, M.. Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), pages 19–27, 1999.Google Scholar

[33] Gossner, H., Russ, C., Siegelin, F., Schneider, J., Schruefer, K., Schulz, T., Duvvury, C., Rinn Cleavelin, C., and Xiong, W.. Unique ESD failure mechanism in a MUGFET technology. In 2006 International Electron Devices Meeting, pages 1–4, 2006.CrossRef Google Scholar

[34] Goyal, A., Whitfield, J., Hong, C., Gill, C., Zhan, C. R., Kushner, V., Gendron, A., and Contractor, S.. Unique ESD failure mechanism of high voltage LDMOS transistors for very fast transients. In 2008 IEEE International Reliability Physics Symposium, pages 673–674, 2008.CrossRef Google Scholar

[35] Grens, C. M.. A comprehensive study of safe-operating-area, biasing constraints, and breakdown in advanced sige HTBS. 2005.Google Scholar

[36] Griffoni, A., Thijs, S., Russ, C., Tremouilles, D., Scholz, M., Linten, D., Collaert, N., Rooyackers, R., Duvvury, C., Gossner, H., Meneghesso, G., and Groeseneken, G.. Impact of strain on ESD robustness of FINFET devices. In 2008 IEEE International Electron Devices Meeting, pages 1–4, 2008.CrossRef Google Scholar

[37] Groppo, E., Gossner, H., and Brederlow, R.. TCAD modeling of ESD diode overshoot during ultrafast TLP events. IEEE Electron Device Letters, 46(3):468–471, 2025.CrossRef Google Scholar

[38] Groppo, E.. ‘Investigation of Novel ESD Device and Circuit Solutions for Advanced Semiconductor Technologies’ PhD Thesis, Technical University Munich, 2026.Google Scholar

[39] Hoffmann, K.. VLSI-entwurf. In VLSI-Entwurf. Oldenbourg Wissenschaftsverlag, 1998.CrossRef Google Scholar

[40] Hower, P. L. and Merchant, S.. Snapback and safe operating area of LDMOS transistors. In International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), pages 193–196, 1999.CrossRef Google Scholar

[41] Hower, P., Tsai, C.-Y., Merchant, S., Efland, T., Pendharkar, S., Steinhoff, R., and Brodsky, J.. Avalanche-induced thermal instability in LDMOS transistors. In Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD ’01 (IEEE Cat. No.01CH37216), pages 153–156, 2001.CrossRef Google Scholar

[42] Hower, P., Pendharkar, S., and Smith, J.. Integrating power devices into silicon roadmaps. IEE Proceedings – Circuits, Devices and Systems, 153:73–78, 2006.CrossRef Google Scholar

[43] Huang, Y.-C. and Ker, M.-D.. A latchup-immune and robust SCR device for ESD protection in 0.25-μm 5-v CMOS process. IEEE Electron Device Letters, 34(5):674–676, 2013.CrossRef Google Scholar

[44] Ille, A., Stadler, W., Pompl, T., Gossner, H., Brodbeck, T., Esmark, K., Riess, P., Alvarez, D., Chatty, K., Gauthier, R., and Bravaix, A.. Reliability aspects of gate oxide under ESD pulse stress. Microelectronics Reliability, 49(12):1407–1416, 2009. Special Section on Electrostatic Discharge Reliability.CrossRef Google Scholar

[45] Industry Council on ESD Target Levels. White paper 2: A case for lowering component level CDM ESD specifications and requirements, 2009.Google Scholar

[46] Industry Council on ESD Target Levels. EOS Part II: Novel perspective of transient AMR. White paper 4, part 2, Industry Council on ESD Target Levels, 2025.Google Scholar

[47] Intel Corporation. Intel architecture day 2020, 2020.Google Scholar

[48] International Organization for Standardization. International standard: ISO 7637, 1990.Google Scholar

[49] Keppens, B., Mergens, M. P. J., Armer, J., Jozwiak, P. C., Taylor, G., Mohn, R., Trinh, C. S., Russ, C. C., Verhaege, K. G., and Ranter, F. D.. Active-area-segmentation (AAS) technique for compact, ESD robust, fully silicided NMOS design. In 2003 Electrical Overstress/Electrostatic Discharge Symposium, pages 1–9, 2003.Google Scholar

[50] Ker, M.-D. and Chang, H.-H.. How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on. Journal of Electrostatics, 47(4):215–248, 1999.CrossRef Google Scholar

[51] Ker, M.-D. and Chen, Z.-P.. SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process. IEEE Transactions on Electron Devices, 51(10):1731–1734, 2004.CrossRef Google Scholar

[52] Ker, M.-D. and Hsu, K.-C.. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits. IEEE Transactions on Device and Materials Reliability, 5(2):235–249, 2005.Google Scholar

[53] Kim, K.-H., Choi, W.-J., and Seo, Y.-J.. Effects of background doping concentration on ESD protection properties of high voltage operation extended drain n-type MOSFET device. In 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, pages 334–341, 2007.CrossRef Google Scholar

[54] Kirk, C. T.. A theory of transistor cutoff frequency (ft) falloff at high current densities. IRE Transactions on Electron Devices, 9(2):164–174, 1962.CrossRef Google Scholar

[55] Lan, T.-Y., Chen, S.-L., Chen, H.-W., and Lee, Y.-M.. Research on ESD protection of ultra-high voltage NLDMOS devices by super-junction engineering in the drain-side drift region. IEEE Journal of the Electron Devices Society, 9:763–773, 2021.CrossRef Google Scholar

[56] Langguth, G., Soldner, W., Ille, A., Cristofoli, A., and Wendel, M.. Thyristor compact model for ESD, DC and RF simulation. In 2013 35th Electrical Overstress/Electrostatic Discharge Symposium, pages 1–10, 2013.Google Scholar

[57] Lee, J.-H., Shih, J. R., Tang, C. S., Liu, K. C., Wu, Y. H., Shiue, R. Y., Ong, T. C., Peng, Y. K., and Yue, J. T.. Novel ESD protection structure with embedded SCR IDMOS for smart power technology. In 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), pages 156–161, 2002.Google Scholar

[58] Lee, C. P., Chau, F. H. F., Ma, W., and Wang, N. L.. The safe operating area of gaas-based heterojunction bipolar transistors. IEEE Transactions on Electron Devices, 53(11):2681–2688, 2006.CrossRef Google Scholar

[59] Lee, J.-H., Su, H.-D., Chan, C.-L., Yang, D.H., Chen, J. F., and Wu, K. M.. The influence of the layout on the ESD performance of HV-LDMOS. In 2010 22nd International Symposium on Power Semiconductor Devices & IC’s (ISPSD), pages 303–306, 2010.Google Scholar

[60] Liang, H., Cao, H., Gu, X., and Guo, Z.. Design and optimization of LDMOS-SCR devices with improved ESD protection performance. Microelectronics Reliability, 61:115–119, 2016.CrossRef Google Scholar

[61] Litzenberger, M., Furbock, C., Pogany, D., Gornik, E., Esmark, K., and Gossner, H.. Investigation of 3d phenomena in the triggering of GG-NMOS electrostatic discharge protection devices. In 30th European Solid-State Device Research Conference, pages 520–523, 2000.CrossRef Google Scholar

[62] Litzenberger, M., Furbock, C., Bychikhin, S., Pogany, D., and Gornik, E.. Scanning heterodyne interferometer setup for the time-resolved thermal and free-carrier mapping in semiconductor devices. IEEE Transactions on Instrumentation and Measurement, 54(6):2438–2445, 2005.CrossRef Google Scholar

[63] Liu, Z., Liou, J. J., and Vinson, J.. Novel silicon-controlled rectifier (SCR) for high-voltage electrostatic discharge (ESD) applications. IEEE Electron Device Letters, 29(7):753–755, 2008.CrossRef Google Scholar

[64] Liu, Z., Vinson, J., Lou, L., and Liou, J. J.. An improved bidirectional SCR structure for low-triggering ESD protection applications. IEEE Electron Device Letters, 29(4):360–362, 2008.Google Scholar

[65] Liu, J., Liu, H., Fan, Y., Zhao, Y., and Liu, C.. A novel high holding voltage ESD device based on SCR and sige. In Journal of Physics: Conference Series, volume 2370, page 012023. IOP Publishing, 2022.Google Scholar

[66] Mergens, M., Wilkening, W., Mettler, S., Wolf, H., Stricker, A., and Fichtner, W.. Analysis and compact modeling of lateral DMOS power devices under ESD stress conditions. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396), pages 1–10, 1999.Google Scholar

[67] Mergens, M. P. J., Wilkening, W., Mettler, S., Wolf, H., Stricker, A., and Fichtner, W.. Analysis of lateral DMOS power devices under ESD stress conditions. IEEE Transactions on Electron Devices, 47(11):2128–2137, 2000.CrossRef Google Scholar

[68] Mergens, M. P. J., Russ, C. C., Verhaege, K. G., Armer, J., Jozwiak, P. C., Mohn, R. P., Keppens, B., and Trinh, C. S.. Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies. IEEE Transactions on Device and Materials Reliability, 5(3):532–542, 2005.CrossRef Google Scholar

[69] Miller, S. L.. Avalanche breakdown in germanium. Physical Review, 99:1234–1241, Aug 1955.CrossRef Google Scholar

[70] Mitros, J., Tsai, C. Y., Shichijo, H., Kunz, K., Morton, A., Goodpaster, D., Mosher, D., and Efland, T.. High-voltage drain extended MOS transistors for 0.18 um logic CMOS process. In 30th European Solid-State Device Research Conference, pages 376–379, 2000.CrossRef Google Scholar

[71] Trivedi, N., Gossner, H., Dhakad, H., Stein, B., and Schneider, J.. An automated approach for verification of onchip interconnect resistance for electrostatic discharge paths. In EOS/ESD Symposium Proceedings, pages 1–8, 2011.Google Scholar

[72] Notermans, G., Kuper, F., and Luchies, J.-M.. Using an SCR as ESD protection without latch-up danger. Microelectronics Reliability, 37(10–11):1457–1460, 1997.CrossRef Google Scholar

[73] Notermans, G., Ritter, H.-M., Holland, S., and Pogany, D.. Dynamic voltage overshoot during triggering of an SCR-type ESD protection. IEEE Transactions on Device and Materials Reliability, 19(4):583–590, 2019.CrossRef Google Scholar

[74] Parthasarathy, V., Khemka, V., Zhu, R., Whitfield, J., Bose, A., and Ida, R.. A double resurf LDMOS with drain profile engineering for improved ESD robustness. IEEE Electron Device Letters, 23(4):212–214, 2002.CrossRef Google Scholar

[75] Parthasarathy, V., Khemka, V., Zhu, R., Whitfield, J., Ida, R., and Bose, A.. Drain profile engineering of resurf LDMOS devices for ESD ruggedness. In Proceedings of the 14th International Symposium on Power Semiconductor Devices and ICS, pages 265–268, 2002.CrossRef Google Scholar

[76] Paul, M., Russ, C., Kumar, B. S., Gossner, H., and Shrivastava, M.. Physics of current filamentation in GGNMOS devices under ESD condition revisited. IEEE Transactions on Electron Devices, 65(7):2981–2989, 2018.CrossRef Google Scholar

[77] Paul, M., Sampath Kumar, B., Russ, C., Gossner, H., and Shrivastava, M.. Challenges & physical insights into the design of fin-based SCRS and a novel FIN-SCR for efficient on-chip ESD protection. IEEE Transactions on Electron Devices, 65(11):4755–4763, 2018.CrossRef Google Scholar

[78] Pendharkar, S., Teggatz, R., Devore, J., Carpenter, J., Efland, T., and Tsai, C.-Y.. SCR-LDMOS. A novel LDMOS device with ESD robustness. In 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), pages 341–344, 2000.CrossRef Google Scholar

[79] Podgaynaya, A., Pogany, D., Gornik, E., and Stecher, M.. Improvement of the electrical safe operating area of a DMOS transistor during ESD events. In 2009 IEEE International Reliability Physics Symposium, pages 437–442, 2009.CrossRef Google Scholar

[80] Russ, C. C., Gossner, H., Schulz, T., Chaudhary, N., Xiong, W., Marshall, A., Duvvury, C., Schrufer, K., and Rinn Cleavelin, C.. ESD evaluation of the emerging MUGFET technology. IEEE Transactions on Device and Materials Reliability, 7(1):152–161, 2007.CrossRef Google Scholar

[81] Russ, C.. Electrostatic Discharge Aspects of FinFETs and other Most Advanced CMOS Technologies, Short Course IEDM 2010.Google Scholar

[82] Salman, A. A., Farbiz, F., Appaswamy, A., Kunz, H., Boselli, G., and Dissegna, M.. Engineering optimal high current characteristics of high voltage DeNMOS. In 2012 IEEE International Reliability Physics Symposium (IRPS), pages 3E.1.1–3E.1.6, 2012.CrossRef Google Scholar

[83] Sarkar, D., Thijs, S., Linten, D., Russ, C., Gossner, H., and Banerjee, K.. A quantitative inquisition into ESD sensitivity to strain in nanoscale CMOS protection devices. In 2010 International Electron Devices Meeting, pages 35.4.1–35.4.4, 2010.CrossRef Google Scholar

[84] Scholz, M., Linten, D., Thijs, S., Sangameswaran, S., Sawada, M., Nakae, T., Hasebe, T., and Groeseneken, G.. ESD on-wafer characterization: Is TLP still the right measurement tool? IEEE Transactions on Instrumentation and Measurement, 58(10):3418–3426, Oct 2009.CrossRef Google Scholar

[85] A. Schenk. Re-examination of physical models in the temperature range 300k–700k. Technical Report, Citeseer, 2001.Google Scholar

[86] Synopsys Inc. Sentaurus Reference Library, Sentaurus Device User Guide. Synopsys Inc., Sunnyvale, CA, USA, v-2024.03 edition, 2024.Google Scholar

[87] Hong-yu, S., Shu-rong, D., Ze-kun, X., Tao, H., Wei, G., and Wei, H.. Improved LDMOS for ESD protection of high voltage BCD process. In 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), pages 1–4, 2019.CrossRef Google Scholar

[88] Shrivastava, M., Bychikhin, S., Pogany, D., Schneider, J., Baghini, M. S., Gossner, H., Gornik, E., and Ramgopal Rao, V.. Filament study of STI type drain extended NMOS device using transient interferometric mapping. In 2009 IEEE International Electron Devices Meeting (IEDM), pages 1–4, 2009.CrossRef Google Scholar

[89] Shrivastava, M., Schneider, J., Baghini, M. S., Gossner, H., and Ramgopal Rao, V.. A new physical insight and 3D device modeling of STI type DeNMOS device failure under ESD conditions. In 2009 IEEE International Reliability Physics Symposium, pages 669–675, 2009.CrossRef Google Scholar

[90] Shrivastava, M., Schneider, J., Baghini, M. S., Gossner, H., and Ramgopal Rao, V.. On the failure mechanism and current instabilities in resurf type DeNMOS device under ESD conditions. In 2010 IEEE International Reliability Physics Symposium, pages 841–845, 2010.CrossRef Google Scholar

[91] Shrivastava, M., Gossner, H., Baghini, M. S., and Ramgopal Rao, V.. Part I: On the behavior of STI-type DeNMOS device under ESD conditions. IEEE Transactions on Electron Devices, 57(9):2235–2242, 2010.Google Scholar

[92] Shrivastava, M., Bychikhin, S., Pogany, D., Schneider, J., Baghini, M. S., Gossner, H., Gornik, E., and Ramgopal Rao, V.. On the differences between 3D filamentation and failure of N & P type drain extended MOS devices under ESD condition. In 2010 IEEE International Reliability Physics Symposium, pages 480–484, 2010.CrossRef Google Scholar

[93] Shrivastava, Mayank, Gossner, Harald, Baghini, Maryam Shojaei, and Ramgopal Rao, V. Part i: On the behavior of sti-type denmos device under esd conditions. IEEE Transactions on Electron Devices, 57(9):2235–2242, 2010.Google Scholar

[94] Shrivastava, M., Gossner, H., Baghini, M. S., and Ramgopal Rao, V.. Part II: On the three-dimensional filamentation and failure modeling of STI type DeNMOS device under various ESD conditions. IEEE Transactions on Electron Devices, 57(9):2243–2250, 2010.Google Scholar

[95] Shrivastava, M., Russ, C., Gossner, H., Bychikhin, S., Pogany, D., and Gornik, E.. ESD robust DeNMOS devices in advanced CMOS technologies. In EOS/ESD Symposium Proceedings, pages 1–10, 2011.Google Scholar

[96] Shrivastava, M. and Gossner, H.. A review on the ESD robustness of drain-extended MOS devices. IEEE Transactions on Device and Materials Reliability, 12(4):615–625, 2012.CrossRef Google Scholar

[97] Shrivastava, M., Gossner, H., and Russ, C.. A drain-extended MOS device with spreading filament under ESD stress. IEEE Electron Device Letters, 33(9):1294–1296, 2012.CrossRef Google Scholar

[98] Smedes, T. and Guitard, N.. Harmful voltage overshoots due to turn-on behavior of ESD protections during fast transients. In 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pages 6A.4-1–6A.4-9, 2007.Google Scholar

[99] Stadler, W., Bargstadt-Franke, S., Brodbeck, T., Gaertner, R., Goroll, M., Gosner, H., and Chr. Muller N. Jensen. From the ESD robustness of products to the system ESD robustness. In 2004 Electrical Overstress/Electrostatic Discharge Symposium, pages 1–8, 2004.CrossRef Google Scholar

[100] Stathis, J. H.. Percolation models for gate oxide breakdown. Journal of Applied Physics, 86(10):5757–5766, 1999.CrossRef Google Scholar

[101] Steinhoff, R. M., Huang, J.-B., Hower, P. L., and Brodsky, J. S.. Current filament movement and silicon melting in an ESD-robust DeNMOS transistor. In 2003 Electrical Overstress/Electrostatic Discharge Symposium, pages 1–10, 2003.Google Scholar

[102] Stricker, A. D., Mettler, S., Wolf, H., Mergens, M., Wilkening, W., Gieser, H., and Fichtner, W.. Characterization and optimization of a bipolar ESD-device by measurements and simulations. Microelectronics Reliability, 39(11):1563–1577, 1999.CrossRef Google Scholar

[103] Strong, A. W., Wu, E. Y., Vollertsen, R.-P., Sune, J., Rosa, G. L., Sullivan, T. D., and Rauch, III, S. E. Reliability Wearout Mechanisms in Advanced CMOS Technologies. Wiley-IEEE Press, Oct 2009.Google Scholar

[104] Suehle, J. S.. Ultrathin gate oxide reliability: Physical models, statistics, and characterization. IEEE Transactions on Electron Devices, 49(6):958–971, 2002.CrossRef Google Scholar

[105] Sun, M. and Lu, Y.. A new ESD protection structure for high-speed GaAs RF ICs. IEEE Electron Device Letters, 26(3):133–135, 2005.Google Scholar

[106] Sze, S. M. and Gibbons, G.. Avalanche breakdown voltages of abrupt and linearly graded p-n junctions in Ge, Si, GaAs, and GaP. Applied Physics Letters, 8(5):111–113, Mar 1966.Google Scholar

[107] Vashchenko, V., Concannon, A., Ter Beek, M., and Hopper, P.. Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits. In Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, pages 181–184, 2002.CrossRef Google Scholar

[108] Vashchenko, V. A. and ter Beek, M.. ESD protection window targeting using LDMOS-SCR devices with p-well-n-well super-junction. In 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual, pages 612–613, 2005.CrossRef Google Scholar

[109] Vashchenko, V. A. and LaFonteese, D. J.. System level and hot plug-in protection of high voltage transient pins. In 2009 31st EOS/ESD Symposium, pages 1–8, 2009.Google Scholar

[110] Vashchenko, V. A., Strachan, A., Linten, D., Lafonteese, D., Concannon, A., Scholz, M., Thijs, S., Jansen, P., Hopper, P., and Groeseneken, G.. Improving the ESD self-protection capability of integrated power NLDMOS arrays. In Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010, pages 1–8, 2010.Google Scholar

[111] Walker, A. J., Ward, S. T., and Puchner, H.. Novel robust high voltage ESD clamps for LDMOS protection. In 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, pages 596–597, 2007.CrossRef Google Scholar

[112] Walker, A. J., Puchner, H., and Dhanraj, S. P.. High-voltage CMOS ESD and the safe operating area. IEEE Transactions on Electron Devices, 56(8):1753–1760, 2009.CrossRef Google Scholar

[113] Wang, C.-T. and Ker, M.-D.. ESD protection design with lateral DMOS transistor in 40-v BCD technology. IEEE Transactions on Electron Devices, 57(12):3395–3404, 2010.CrossRef Google Scholar

[114] Wang, Z., Klebanov, M., Cooper, R. B., Liang, W., Courtney, S., and Liou, J. J.. No-snapback silicon-controlled rectifier for electrostatic discharge protection of high-voltage ICS. IEEE Electron Device Letters, 36(11):1121–1123, 2015.CrossRef Google Scholar

[115] Wang, Z., Qi, Z., Liang, L., Qiao, M., Li, Z., and Zhang, B.. Novel high holding voltage SCR with embedded carrier recombination structure for latch-up immune and robust ESD protection. Nanoscale Research Letters, Dec, 14 2019.CrossRef Google Scholar

[116] Yadav, M., Vaidya, M., and Shrivastava, M.. Proposal to achieve the ultimate holding voltage tunability in silicon controlled rectifiers (SCRS) for a wide range of ESD protection application. In 2025 IEEE International Reliability Physics Symposium (IRPS), pages 1–5, 2025.CrossRef Google Scholar

[117] Yadav, M.. Private communication.Google Scholar

[118] Wunsch, D. C. and Bell, R. R.. Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages. IEEE Transactions on Nuclear Science, 15(6):244–259, 1968.CrossRef Google Scholar

[119] Yoffa, E. J.. Screening of hot-carrier relaxation in highly photoexcited semiconductors. Physical Review B, 23:1909–1919, Feb 1981.Google Scholar

[120] Egawa, H.. Avalanche characteristics and failure mechanism of high voltage diodes. IEEE Transactions on Electron Devices, ED-13(11):754–758, Nov 1966.Google Scholar

[121] Kholodnov, V. and Nikitin, M.. Physical design fundamentals of high-performance avalanche heterophotodiodes with separate absorption and multiplication regions. 2012.Google Scholar

[122] Pendharkar, S., Hower, P., Steinhoff, R., Brodsky, J., Devore, J., and Grose, B.. Using two-dimensional filament modeling to predict LDMOS and SCRLDMOS behavior under high current ESD conditions. In Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, Osaka, Japan, 2001.Google Scholar

[123] Fujiwara, S., Nakaya, K., Hirano, T., Okuda, T., and Watanabe, Y.. Source engineering for ESD robust NLDMOS. In EOS/ESD Symposium Proceedings, Oct 2011.Google Scholar

[124] Hower, P. and Reddy, G. K.. Avalanche injection and second breakdown in transistors. IEEE Transactions on Electron Devices, ED-17:320–335, 1970.CrossRef Google Scholar

[125] Chung, Y., Xu, H., Ida, R., Min, W.-G., and Baird, B.. ESD scalability of LDMOS devices for self-protected output drivers. In Proceedings of ISPSD ’05 – The 17th International Symposium on Power Semiconductor Devices and ICs, 2005.Google Scholar

[126] Dai, C.-T. and Ker, M.-D.. ESD protection design with stacked high-holding-voltage SCR for high-voltage pins in a battery-monitoring IC. IEEE Transactions on Electron Devices, 63(5):1966–2002, May 2016.Google Scholar

[127] Voldman, S.. The ESD handbook. Wiley Semiconductors, 2021.Google Scholar

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