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A Single Chip Integrated Navigation System

Published online by Cambridge University Press:  21 October 2009

Eric Aardoom  and
André Nieuwland
Eric Aardoom
Affiliation:
(Delft University of Technology)
André Nieuwland
Affiliation:
(Delft University of Technology)
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Abstract

Recently, integration of different radionavigation systems has become very popular, since it improves system integrity, availability, accuracy and reliability. This paper discusses a new, flexible and cost-effective approach to system integration, centred on a single-chip application specific processor (ASP). An overview of this integrated system is presented and the application of the ASP for the implementation of a six-channel GPS, OMEGA, Loran-C and MLS receiver is given. The ASP is currently being implemented on a 180000 transistor 1·6μ, m CMOS Sea of Gates chip, and is expected to run at 100 MHz clock speed.

Keywords

1. Integrated systems2. Computers3. Air navigation

Information

Type
Research Article
Information
The Journal of Navigation , Volume 46 , Issue 1 , January 1993 , pp. 95 - 104
Copyright
Copyright © The Royal Institute of Navigation 1993

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References

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