Hostname: page-component-7b7567c8c-2n9c9 Total loading time: 0 Render date: 2026-11-15T22:49:14.742Z Has data issue: false hasContentIssue false

Modeling and simulations of high-power microwave devices using the CHIPIC code

Published online by Cambridge University Press:  08 October 2012

JUN ZHOU
Affiliation:
School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu 610054, People's Republic of China (zhoujun@uestc.org)
D. G. LIU
Affiliation:
School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu 610054, People's Republic of China (zhoujun@uestc.org)
C. LIAO
Affiliation:
School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu 610054, People's Republic of China (zhoujun@uestc.org)
Rights & Permissions [Opens in a new window]

Abstract

Core share and HTML view are not available for this content. However, as you have access to this content, a full PDF is available via the 'Save PDF' action button.

The CHIPIC code, a fully electromagnetic particle-in-cell (PIC) code for modeling and simulations of high-power microwave (HPM) devices, is introduced in this paper. It consists of a two-dimensional (2D) code and a three-dimensional (3D) code. The 2D code can model and simulate HPM devices with symmetric structure on 2D Cartesian, cylindrical and polar grids, while the 3D code can model and simulate HPM devices on 3D Cartesian and cylindrical grids. The fields are calculated using the finite-difference time-domain scheme, and the particles are described by the PIC scheme. Various types of boundary conditions have also been implemented for different kinds of applications. In addition, the 3D code is specifically designed for high-performance modeling and computing. It uses the message passing interface and the open specifications for multiprocessing (OpenMP) for parallelization. Its parallel design ensures that it is capable of efficiently executing on a variety of architectures. In order to allow efficient use of parallel architectures, it provides automated partitioning and dynamic load balancing. Even though this code is still in development, it has successfully simulated various real-world HPM experimental devices. Simulation results on some typical HPM devices by using the CHIPIC code are given, which agree well with those obtained from some well-known PIC codes. Direction for future work is also presented.

Information

Type
Papers
Copyright
Copyright © Cambridge University Press 2012