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On the operating unit size of load/store architectures†

Published online by Cambridge University Press:  04 February 2010

J. A. BERGSTRA and
C. A. MIDDELBURG
J. A. BERGSTRA
Affiliation:
Informatics Institute, University of Amsterdam, Science Park 904, 1098 XH Amsterdam, the Netherlands Email: J.A.Bergstra@uva.nl, C.A.Middelburg@uva.nl
C. A. MIDDELBURG
Affiliation:
Informatics Institute, University of Amsterdam, Science Park 904, 1098 XH Amsterdam, the Netherlands Email: J.A.Bergstra@uva.nl, C.A.Middelburg@uva.nl
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Abstract

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We introduce a strict version of the concept of a load/store instruction set architecture in the setting of Maurer machines. We take the view that transformations on the states of a Maurer machine are achieved by applying threads as considered in thread algebra to the Maurer machine. We study how the transformations on the states of the main memory of a strict load/store instruction set architecture that can be achieved by applying threads depend on the operating unit size, the cardinality of the instruction set and the maximal number of states of the threads.

Information

Type
Paper
Information
Mathematical Structures in Computer Science , Volume 20 , Issue 3 , June 2010, pp. 395 - 417
Copyright
Copyright © Cambridge University Press 2010

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