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3D Process Integration – Requirements and Challenges

Published online by Cambridge University Press:  01 February 2011

Juergen Max Wolf,
Armin Klumpp,
Kai Zoschke,
Robert Wieland,
Lars Nebrich,
Matthias Klein,
Hermann Oppermann,
Peter Ramm,
Oswin Ehrmann and
Herbert Reichl
Juergen Max Wolf
Affiliation:
Juergen.Wolf@izm.fraunhofer.de, Fraunhofer IZM, Germany
Armin Klumpp
Affiliation:
armin.klumpp@izm-m.fraunhofer.de, Fraunhofer IZM, München, Germany
Kai Zoschke
Affiliation:
kai.zoschke@izm.fraunhofer.de, Fraunhofer IZM, Germany
Robert Wieland
Affiliation:
robert.wieland@izm-m.fraunhofer.de, Fraunhofer IZM, Germany
Lars Nebrich
Affiliation:
lars.nebrich@izm-m.fraunhofer.de, Fraunhofer IZM, Germany
Matthias Klein
Affiliation:
matthias.klein@izm.fraunhofer.de, Fraunhofer IZM, Germany
Hermann Oppermann
Affiliation:
Hermann.oppermann@izm.fraunhofer.de, Fraunhofer IZM, Germany
Peter Ramm
Affiliation:
Peter.Ramm@izm-m.fraunhofer.de, Fraunhofer IZM, Germany
Oswin Ehrmann
Affiliation:
oswin.ehrmann@izm.fraunhofer.de, Fraunhofer IZM, Germany
Herbert Reichl
Affiliation:
herbert.reichl@izm.fraunhofer.de, Fraunhofer IZM, Germany
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Abstract

Heterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market.The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

Keywords

thin filmelectrodepositionpackaging

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1112: Symposium E – Materials and Technologies for 3-D Integration , 2008, 1112-E01-01
Copyright
Copyright © Materials Research Society 2009

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References

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