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Copper Metallization Manufacturing Issues for Future ICs

Published online by Cambridge University Press:  25 February 2011

Ronald J. Gutmann,
T. Paul Chow,
William N. Gill,
Alain E. Kaloyeros,
William A. Lanford and
Shyam P. Murarka
Ronald J. Gutmann
Affiliation:
Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180
T. Paul Chow
Affiliation:
Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180
William N. Gill
Affiliation:
Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180
Alain E. Kaloyeros
Affiliation:
University at Albany-SUNY, Albany, NY 12222
William A. Lanford
Affiliation:
University at Albany-SUNY, Albany, NY 12222
Shyam P. Murarka
Affiliation:
Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180
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Abstract

Copper metallization for on-chip multilevel interconnects is receiving increasing attention for future generations of ICs, with advantages of low line resistance, low interconnect delay, high electromigration resistance and, possibly, overall back-end process simplicity. However, copper introduces a set of processing and manufacturing issues which must be addressed in the research and development phases of the technology. This paper summarizes the most likely processing steps for integrating copper metallization into IC technology and presents the manufacturing issues (materials, unit processing and process integration issues) that need to be addressed.

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References

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