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Design and Process Issues for Silicon Carbide Power DiMOSFETS

Published online by Cambridge University Press:  21 March 2011

Sei-Hyung Ryu,
Anant K. Agarwal,
Nelson S. Saks,
Mrinal K. Das,
Lori A. Lipkin,
Ranbir Singh and
John W. Palmour
Sei-Hyung Ryu
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
Anant K. Agarwal
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
Nelson S. Saks
Affiliation:
Navel Research Laboratory, 4555 Overlook Avenue Washington, D.C. 20375
Mrinal K. Das
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
Lori A. Lipkin
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
Ranbir Singh
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
John W. Palmour
Affiliation:
Cree, Inc., 4600 Silicon Drive Durham, NC 27703
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Abstract

This paper discusses the design and process issues of high voltage power DiMOSFETs (Double implanted MOSFETs) in 4H-silicon carbide (SiC). Since Critical Field (E C ) in 4H-SiC is very high (10X higher than that of a Si), special care is needed to protect the gate oxide. 2D device simulation tool was used to determine the optimal JFET gap, which provides adequate gate oxide protection as well as a reasonable JFET resistance. The other issue in 4H-SiC DiMOSFETs is extremely low effective channel mobility (μeff ) in the implanted p-well regions. NO anneal of the gate oxide and buried channel structure are used for increasing μeff . NO anneal, which was reported to be very effective in increasing the μeff of SiC MOSFETS in p-type epilayers, did not produce reasonable μeff of SiC MOSFETs in the implanted p-well. Buried channel (BC) structure with 2.7×1012 cm−2 charge in the channel showed high μeff utilizing bulk buried channel, but resulted in a normally-on device. However, it was shown that by controlling the charge in the BC layer, a normally off device with high μeff can be produced. A 3.3 mm × 3.3 mm DiMOSFET with BC structure showed a drain current of 10 A, which is the highest current reported in SiC power MOSFETs to date, at a forward drop of 4.4 V with a gate bias of only 2.5 V.

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References

REFERENCES

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