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Ge nanocrystals in MOS-memory structures produced by molecular-beam epitaxy and rapid-thermal processing

Published online by Cambridge University Press:  01 February 2011

A. Nylandsted Larsen
Affiliation:
Institute of Physics and Astronomy, University of Aarhus, DK-8000 Aarhus C, Denmark
A. Kanjilal
Affiliation:
Institute of Physics and Astronomy, University of Aarhus, DK-8000 Aarhus C, Denmark
J. Lundsgaard Hansen
Affiliation:
Institute of Physics and Astronomy, University of Aarhus, DK-8000 Aarhus C, Denmark
P. Gaiduk
Affiliation:
Institute of Physics and Astronomy, University of Aarhus, DK-8000 Aarhus C, Denmark
P. Normand
Affiliation:
Institute of Microelectronics, NCSR Demokritos, 15310 Aghia Paraskevi, Greece
P. Dimi-trakis
Affiliation:
Institute of Microelectronics, NCSR Demokritos, 15310 Aghia Paraskevi, Greece
D. Tsoukalas
Affiliation:
National Technical University Athens, School of Applied Sciences, 15780 Zografou, Greece
N. Cherkashin
Affiliation:
CEMES/CNRS, 29 rue J. Marvig, BP4347, F-31055, Toulouse, France
A. Claverie
Affiliation:
CEMES/CNRS, 29 rue J. Marvig, BP4347, F-31055, Toulouse, France
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Abstract

A method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTP) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×1012 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved.

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