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Influence of Interface States on High Temperature SiC Sensors and Electronics

Published online by Cambridge University Press:  11 February 2011

Ruby N. Ghosh
Affiliation:
Center for Sensor Materials, Michigan State Univ., East Lansing, MI 48824–2320
Peter Tobias
Affiliation:
Center for Sensor Materials, Michigan State Univ., East Lansing, MI 48824–2320
Brage Golding
Affiliation:
Center for Sensor Materials, Michigan State Univ., East Lansing, MI 48824–2320Dept. of Physics & Astronomy, Michigan State Univ., East Lansing, MI 48824–2320
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Abstract

Silicon carbide based metal/oxide/semiconductor (MOS) devices are well suited for operation in chemically reactive high temperature ambients. The response of catalytic gate SiC MOS sensors to hydrogen-containing species has been assumed to be due to the formation of a dipole layer at the metal/oxide interface, which gives rise to a voltage translation of the high frequency capacitance voltage (C-V) curve. From in-situ C-V spectroscopy, performed in a controlled gaseous environment, we have discovered that high temperature (800 K) exposure to hydrogen results in (i) a flat band voltage occurring at a more negative bias than in oxygen and (ii) the transition from accumulation to inversion occurring over a relatively narrow voltage range. In oxygen, this transition is broadened indicating the creation of a large number of interface states. We interpret these results as arising from two independent phenomena – a chemically induced shift in the metal/semiconductor work function difference and the passivation/creation of charged states (DIT) at the SiO2/SiC interface. Our results are important for both chemical sensing and electronic applications. MOS capacitance gas sensors typically operate in constant capacitance mode. Since the slope of the C-V curve changes dramatically with gas exposure, we discuss how sensor-to-sensor reproducibility and device response time are influenced by the choice of operating point. For electronic applications understanding the environmentally induced changes in DIT is crucial to designing drift-free MOS devices. Our results are applicable to n-type SiC MOS devices in general, independent of the specifics of sample fabrication.

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