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Interconnect Capacitance Extraction in Large-Area a-Si Imaging Systems

Published online by Cambridge University Press:  10 February 2011

H.H. Pham and
A. Nathan
H.H. Pham
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1
A. Nathan
Affiliation:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1
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Abstract

We present a new numerical extraction method for the quasi-static parasitic coupling capacitances associated with geometric overlapping in amorphous silicon (a-Si) thin film transistors (TFTs) and interconnect addressing lines in large-area a-Si imaging systems. The capacitance is extracted using a recently developed computational technique, based on exponential expansion of the Green's function, which offers a quick and accurate means of computing the three-dimensional potential and electric field, and hence, the charge distribution and capacitance. The technique can be used for effectively dealing with the extreme geometry TFT and interconnect structures (where layer thicknesses are much smaller than the other physical dimensions), the floating potential of the glass substrate, and multidielectric media, all of which are typical to large-area a-Si imaging electronics.

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References

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