Hostname: page-component-7b7567c8c-2n9c9 Total loading time: 0 Render date: 2026-11-14T23:33:21.402Z Has data issue: false hasContentIssue false
  • English
  • Français

New Method to Characterize Thin Oxide Reliability

Published online by Cambridge University Press:  15 February 2011

Heng-Chih Lin,
J. P. Snyder and
C. R. Helms
Heng-Chih Lin
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
J. P. Snyder
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
C. R. Helms
Affiliation:
Department of Electrical Engineering, Stanford University, Stanford, CA 94305
Get access

Abstract

Next generation ULSI devices will require ultra thin gate insulators where degradation due to contamination or surface microroughness is an even more important problem. Tunneling and breakdown characteristics are critical electrical testing methods, but unfortunately obtaining meaningful oxide integrity information on the one hand and tunneling IV's on the other is a tedious and time consuming process.

In this research, we report on a new method to measure meaningful IV's, Q bd 's, and V bd 's at the same time. This method uses a linear current ramp strategy where a voltage ramp to between 8–10 MV/cm is applied first followed by a linear current ramp until breakdown is reached. There are several advantages of this new method: The linear voltage ramp quickly and easily identifies low breakdown devices, whereas switching to a linear current ramp provides for nearly constant field stressing to obtain meaningful IV and Q bd

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

1. Meindl, J. D., De, V.K. and Agrawal, B., Proc. IEEE Intern. Solid-State Circuits Conf. - ISSCC '93, pp. 124 (1993).Google Scholar
2. Schuegraf, K.F. and Hu, Chenming, Proc. of IEEE VLSI Tech. Symp., pp. 43 (1993).Google Scholar
3. Dumin, D.J., Maddux, J.R., Scott, R.S. and Subramoniam, R., IEEE Trans. Electron Devices 41(9), 1570 (1994).Google Scholar
4. Subramoniam, R., Scott, R.S., and Dumin, D.J., Proc. IEEE Intern. Electron Devices Meeting, pp. 135 (1992).Google Scholar
5. Apte, P. P. and Saraswat, K.C., IEEE Electron Device Letters 14(11), 512 (1993).Google Scholar
6. Abadeer, W. W., Vollertsen, R. P., Bolam, R. J., DiMaria, D. J. and Cartier, E., Proc. 1994 VLSI Tech. Symp., pp. 43 (1994).Google Scholar
7. Kao, D.B., deLarios, J.M., Helms, C.R. nad Deal, B.E., 27th Annual Proc. Reliability Phys. 1989, pp. 9 (1989).Google Scholar
8. Apte, P.P., Kubota, T. and Saraswat, K.C., J. Electrochem. Soc. 140(5), 770 (1993).Google Scholar
9. Ohmi, T., Nakamura, K. and Makihara, K., Proc. of 1994 IEEE Intern. Reliability Phy. Symp., pp. 161 (1994).Google Scholar
10. Cappelletti, P., Ghezzi, P., Pio, F., and Riva, C., Proc. IEEE 1991 Int. Conf. on Microelectronic Test Structure, 4(1), pp. 81,(1991).Google Scholar