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Nonvolatile Power-Gating FPGA Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque MTJs

Published online by Cambridge University Press:  15 June 2012

Shuu’ichirou Yamamoto,
Yusuke Shuto and
Satoshi Sugahara
Shuu’ichirou Yamamoto
Affiliation:
Department of Information Processing, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, JapanCREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
Yusuke Shuto
Affiliation:
Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, JapanCREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
Satoshi Sugahara
Affiliation:
Imaging Science and Engineering Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8503, JapanCREST, Japan Science and Technology Agency, 4-1-8 Hon-cho, Kawaguchi 332-0012, Japan
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Abstract

We proposed and computationally analyzed a nonvolatile power-gating field programmable gate array (NVPG-FPGA) based on pseudo-spin-transistor architecture with spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The circuit employs nonvolatile static random memory (NV-SRAM) cells and nonvolatile flip-flops (NV-FFs) as the storage circuits. The circuit configuration and microarchitecture are compatible with SRAM-based FPGAs, and the additional nonvolatile memory functionality makes it possible to execute efficient power-gating (PG). Break-even time (BET) for the nonvolatile configuration logic block (NV-CLB) of the NVPG-FPGA was also analyzed, and reduction techniques of the BET were proposed, which allows highly efficient PG operations with a fine granularity.

Keywords

devicesmemorymagnetoresistance (transport)

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References

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