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A Patterned Soi by Masked Anneal for System-on-Chip Applications

Published online by Cambridge University Press:  15 March 2011

G. M. Cohen and
D. K. Sadana
G. M. Cohen
Affiliation:
IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A
D. K. Sadana
Affiliation:
IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598, U.S.A
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Abstract

We present a method for fabricating pattern silicon-on-insulator (SOI) wafers that exploit internal thermal oxidation (ITOX) to control the BOX formation. We demonstrated the process by fabricating a pattern SOI having two different buried oxides (BOX) thickness. We also show that by using a very low oxygen dose the BOX can be quenched in the masked regions, while maintaining a continuous BOX in unmasked regions. Very low damage forms at the transition region from thick to thin BOX. Due to the oxygen diffusion the smallest patterned box feature we could obtain was limited to > 0.5 micron.

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References

References:

1. Mandelman, J. A., Barth, J. E., DeBrosse, J. K., Dennard, R.H., Kalter, H.L., Gautier, J. and Hanafi, H.I., IEEE Int. SOI Conference, p. 136, (1996).Google Scholar
2. Hannon, R., Iyer, S.K., Sadana, D., Rice, J.P., Ho, H.L., Khan, B.A., and Iyer, S. S., 2000 Symposium on VLSI Technology, p. 66, (2000).Google Scholar
3. Cohen, G.M. and Sadana, D. K., U.S. Patent No. 6 300 218 (9 October 2001).Google Scholar
4. Sadana, D.K. and Souza, J.P. de, U.S. Patent No. 5 930 643 (27 July 1999).Google Scholar