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Process and Device Considerations for Small Grain Polysilicon Transistors

Published online by Cambridge University Press:  28 February 2011

H. Shichijo,
S.D.S. Malhi,
R. Sundaresan,
S.K. Banerjee and
H.W. Lam
H. Shichijo
Affiliation:
Texas Instruments Inc., P.O.Box 225621, MS 369, Dallas, Texas 75265
S.D.S. Malhi
Affiliation:
Texas Instruments Inc., P.O.Box 225621, MS 369, Dallas, Texas 75265
R. Sundaresan
Affiliation:
Texas Instruments Inc., P.O.Box 225621, MS 369, Dallas, Texas 75265
S.K. Banerjee
Affiliation:
Texas Instruments Inc., P.O.Box 225621, MS 369, Dallas, Texas 75265
H.W. Lam
Affiliation:
Texas Instruments Inc., P.O.Box 225621, MS 369, Dallas, Texas 75265
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Abstract

Polysilicon transistors offer the first entry into 3-dimensional ICs. This paper reviews some process and device considerations in using these devices in VLSI environments. The process issues include the choice of polysilicon grain size, layer thickness, doping, and methods of grain boundary passivation. The device considerations are closely related to the effects of grain boundaries in modifying the device characteristics. Three specific application examples are reviewed. It is concluded that polysilicon transistors offer new possibilities to enhance the performance of bulk technologies without resorting to any recrystallization techniques.

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Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 53 , 1985, 419
Copyright
Copyright © Materials Research Society 1986

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References

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