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Silicides for the 65 nm Technology Node

Published online by Cambridge University Press:  01 February 2011

Paul R. Besser,
Simon Chan,
Eric Paton,
Thorsten Kammler,
David Brown,
Paul King and
Laura Pressley
Paul R. Besser
Affiliation:
Technology Development Group, Advanced Micro Devices, Inc. One AMD Place, Mail stop 36, Sunnyvale, CA 94087 USA
Simon Chan
Affiliation:
FASL LLC, Advanced Micro Devices, Sunnyvale, CA
Eric Paton
Affiliation:
FASL LLC, Advanced Micro Devices, Sunnyvale, CA
Thorsten Kammler
Affiliation:
AMD Saxony LLC & Co KG, Dresden, Germany
David Brown
Affiliation:
Advanced Micro Devices, East Fishkill, NY
Paul King
Affiliation:
FASL LLC, Advanced Micro Devices, Sunnyvale, CA
Laura Pressley
Affiliation:
FASL LLC, Advanced Micro Devices, Austin, TX
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Abstract

At the 65 nm node, silicide faces formidable challenges. Co is the current process of record for most integrated circuit manufacturers and thus becomes baseline silicide for 65 nm. However, Ni is the likely replacement. Both silicides are challenged to meet the requirements at the 65 nm node. This manuscript reviews the current CoSi2 challenges (dopant interactions, Ge interactions, linewidth extendibility, impurity effects, agglomeration issues, etc). Ni consumes less Si but has its own challenges, including issues with contact leakage and thermal budget, excessive diffusion and oxidation, interactions with dopant and impurities. Both silicides have formation and stability issues in the presence of Ge. Additions of Ge increase the temperature at which a low resistance CoSi2 is formed due to film segregation into CoSi2 and Ge-rich Si-Ge grains. With Ni, additions of Ge decrease the temperature at which NiSi converts to a NiSi2, lead to agglomeration at a lower temperature and lead to germanosilicide formation.

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