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Thin (100 nm) SOS for Application to Beyond VLSI Microelectronics

Published online by Cambridge University Press:  28 February 2011

Ronald E. Reedy and
Graham A. Garcia
Ronald E. Reedy
Affiliation:
Naval Ocean Systems Center, Code 553, San Diego, CA, 92152-5000
Graham A. Garcia
Affiliation:
Naval Ocean Systems Center, Code 553, San Diego, CA, 92152-5000
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Abstract

Of the numerous requirements for advanced VLSI silicon microelectronics, power dissipation per unit area, speed, packing density and radiation hardness are especially important. Power dissipation and speed have forced an evolutionary path from PMOS to NMOS to NMOS E/D and to the currently used CMOS. As evidenced by the large number of publications, CMOS on an insulating substrate is receiving increased attention due to its potential as the next generation in MOS evolution. We review results of our previous and current research in silicon on sapphire (SOS) which has led to high quality ultrathin SOS (<100 nm thick) appropriate for high density CMOS circuitry. Basic materials developments, device performance, and CMOS design considerations in 100 nm thick improved SOS will be discussed.

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References

1 For background on SOS, several review references are recommended: Ipri, Alfred C., in Silicon Integrated Circuits, Part A. ed. by Kahng, Davon (Academic Press, Inc., New York, 1981), 253–395; I. Golecki in Comparison of Thin Film Transistor SOI Technologies, Materials Research Society, 1984 Spring Meeting, Albuquerque, Feb., 1984.CrossRefGoogle Scholar
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