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A Closer “Look” at Modern Gate Oxides

Published online by Cambridge University Press:  14 March 2011

Frieder H. Baumann,
C.-P. Chang,
John L. Grazul,
Avid Kamgar,
C. T. Liu and
David A. Muller
Frieder H. Baumann
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
C.-P. Chang
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
John L. Grazul
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
Avid Kamgar
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
C. T. Liu
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
David A. Muller
Affiliation:
Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974
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Abstract

Using high resolution TEM (HRTEM), we identified some process induced ‘weak spots’ in SiO2 layers: First, we observed thinning in the periphery of the transistor, i. e. near the boundary to the shallow trench isolation. At the boundary to the shallow trench, the Si substrate gradually changes its orientation from <100> to <110>, which results in an unexpected oxidation behavior in this region. Secondly, we observed the intrusion of poly-Si grains from the gate into the gate oxide, resulting in local thinning of the dielectric. Using image simulations, we show that conventional high resolution TEM can reveal the interface roughness only to a very limited extend.

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References

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