Hostname: page-component-7b7567c8c-fvjsw Total loading time: 0 Render date: 2026-11-14T12:58:37.923Z Has data issue: false hasContentIssue false
  • English
  • Français

CMOS/SOS VLSI Technology

Published online by Cambridge University Press:  21 February 2011

Tai Sato,
Jun Iwamura,
Hiroyuki Tango and
Katsuyuki Doi
Tai Sato
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Jun Iwamura
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Hiroyuki Tango
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Katsuyuki Doi
Affiliation:
Toshiba Corporation, Kawasaki, JAPAN
Get access

Abstract

CMOS is considered as a prospective technology in the VLSI era because of its low power consumption and high driving capability. While ordinary bulk silicon CMOS devices are inferior to SOS CMOS devices in chip area, operation speed and latch-up problem due to the need for isolation wells. SOS is an inherent good partner of the CMOS circuits owing to the simple and perfect isolation. SOS technology, however, has the problem of high wafer cost. Consequently, SOS technology is best applied to high performance logic devices. Latest results of 8k-gate CMOS/SOS gate array and 16×16bit multipliers show 0.87ns 2-NAND gate delay and 27ns multiplication time, respectively, which compete with ECL devices. Application of SOS devices down to 1μm is also promising for very high speed operation. A 78ps gate delay is achieved by double solid phase epitaxy and 1μm technology. INTRO

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

1. Manasevit, H.M. and Simpson, W.I.: J.Appl.Phys. 35, 1349–1351 (1964).Google Scholar
2. Sato, T., Takeishi, Y. and Hara, H.: Phys.Rev.B 947–956 (1968).Google Scholar
3. Schlötterer, H.: Solid-State Electron. 11, 947–956 (1968).Google Scholar
4. Ohmura, Y., Shibata, K., Inoue, T., Yoshii, T.: IEEE Electron Device Lett. EDL–4, 57 (1983).10.1109/EDL.1983.25646Google Scholar
5. Lau, S.S.,Matteson, S., Mayer, J.W., Revesz, P., Gyulai, J., Roth, J., Sigmon, T.W. and Cass, T.: Appl.Phys.Lett. 34, 76–79 (1979).10.1063/1.90564Google Scholar
6. Yoshil, T., Taguchi, S., Inoue, T. and Tango, H.: Japanese J. of Applied Physics. 21, 175 (1982).10.7567/JJAPS.21S1.175Google Scholar
7. Lee, J.Y., Mayer, D.C. and Vasudev, P.K.: IEDM Digest of Technical Papers. 376–379 (Dec.1983).Google Scholar
8. Duffy, M.T. et.al.: J.Cryst.Growth. 58, 10 (1982).10.1016/0022-0248(82)90205-6Google Scholar
9. Iwamura, J., Ohashi, M., Isobe, M., Hanada, M., Sugino, E., Maeguchi, K., Sato, T. and Tango, H.: Proc. 10th Conf. Solid State Devices, Tokyo, 1978, Japanese J. of Applied Physics. 18 Suppl.18–1. 63–69 (1979).Google Scholar
10. Iwamura, J., Kinoshita, T., Sugai, M., Tango, H., Sato, T., Miyata, M. and Ohmori, Y.: ISSCC Digest of Technical Papers, 224–225,275 (Feb.1981).Google Scholar
11. Tanaka, S. et. al.: ISSCC Digest of Technical Papers, 260–261 (Feb. 1984).Google Scholar
12. Iwamura, J. et. al.: ISSCC Digest of Technical Papers., 92–93 (Feb. 1984).Google Scholar
13. Yoshida, M., Nakahara, M., Taguchi, S., Maeguchi, K. and Tango, H.: IEDM Digest of Technical Papers. 372–375 (Dec.1983).Google Scholar