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Defect Analyses in VLSI Devices by TEM Observation and Process Simulation

Published online by Cambridge University Press:  03 September 2012

H. Mikoshiba,
N. Nishio,
T. Matsumoto,
H. Kikuchi,
T. Kitano and
H. Kaneko
H. Mikoshiba
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
N. Nishio
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
T. Matsumoto
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
H. Kikuchi
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
T. Kitano
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
H. Kaneko
Affiliation:
NEC Corporation, VLSI Development Division, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan
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Abstract

This paper presents several examples of defect analyses carried out in actual VLSI failure analyses and experiments, using TEM technique, process simulation and other advanced analytical tools. New TEM techniques are also described to observe a precise location which has failed.

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References

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