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Fundamental Limits for 3D Wafer-to-Wafer AlignmentAccuracy

Published online by Cambridge University Press:  17 March 2011

M. Wimplinger,
J.-Q. Lu,
J. Yu,
Y. Kwon,
T. Matthias,
T.S. Cale and
R.J. Gutmann
M. Wimplinger
Affiliation:
EV Group, E. Thallner Str. 1, 4780 Schaerding, Austria
J.-Q. Lu
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180, luj@rpi.edu
J. Yu
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
Y. Kwon
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
T. Matthias
Affiliation:
EV Group Inc., 3701, E. University Dr., Phoenix, AZ 85034, m.wimplinger@EVGroup.com
T.S. Cale
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
R.J. Gutmann
Affiliation:
Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180
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Abstract

Wafer-level three-dimensional (3D) integration as an emerging architecturefor future chips offers high interconnect performance by reducing delays ofglobal interconnects and high functionality with heterogeneous integrationof materials, devices, and signals. Various 3D technology platforms havebeen investigated, with different combinations of alternative alignment,bonding, thinning and inter-wafer interconnection technologies. Precisealignment on the wafer level is one of the key challenges affecting theperformance of the 3D interconnects. After a brief overview of thewafer-level 3D technology platforms, this paper focuses on waferto-waferalignment fundamentals. Various alignment methods are reviewed. A higheremphasis lies on the analysis of the alignment accuracy. In addition to thealignment accuracy achieved prior to bonding, the impacts of wafer bondingand subsequent wafer thinning will be discussed.

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References

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