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Future Directions of Non-volatile Memory Technologies

Published online by Cambridge University Press:  01 February 2011

Albert Fazio
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Abstract

It expected that for many years to come, the majority of the nonvolatile memories shipped will be based on current mainstream flash technologies, which utilize transistor based charge storage memory cells and multi-level-cell concepts, for storing more than one logic bit in a single physical cell. Moore's law will continue to drive transistor based memory technology scaling but technology complexity will be increasing. In order to meet technology scaling, the mainstream transistor based flash technologies will start evolving to incorporate material and structural innovations. This paper will review the current status and discuss the approaches being explored to provide scaling solutions for future transistor based non-volatile memory products. Based on the introduction of material innovations, it is expected that the planar transistor based flash memory cell can scale into the 32nm node. Further, more complex, structural innovations will be required to maintain further scaling. New memory concepts, not relying on transistors as a basis of the memory cell, provide new opportunities for future low cost memories. Several of these new concepts will be summarized and contrasted with the mainstream transistor based flash memory technologies.

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References

REFERENCES

1. Brown, W., Brewer, J., Nonvolatile Semiconductor Memory Technology A Comprehensive Guide to Understanding and Using NVSM Device, IEEE Press, New York Google Scholar
2. Kynett, V.N., Baker, A.; Fandrich, M.L.; Hoekstra, G.P.; Jungroth, O.; Kreifels, J.A.; Wells, S.; Winston, M.D.; “An In-System Reprogrammable 256K CMOS Flash Memory,” Technical Digest IEEE International Solid State Circuits Conference, 1988, pp. 132–133.Google Scholar
3. She, M., King, T.J., Hu, C., Zhu, W., Luo, Z., Han, J.P., Ma, T.P.; “Low-voltage, fastprogramming P-channel flash memory with JVD tunneling nitride,” Semiconductor Device Research Symposium, 2001 International, 5–7 Dec. 2001. Pages: 641–644 Google Scholar
4. Pein, H.B., Plummer, J.D.; “Performance of the 3-D sidewall flash EPROM cell”, Electron Devices Meeting, 1993. Technical Digest., International, 5–8 Dec. 1993, pp.11–14 Google Scholar
5. Naruke, K., Taguchi, S.; Wada, M.; “Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness”, 1988 IEDM Tech. Dig., pp. 424 Google Scholar
6. Korotkov, A., Likharev, K.; “Resonant Fowler-Nordheim Tunneling through Layered Tunnel Barriers and its Possible Applications”, 1999 IEDM Tech. Dig., pp. 223–226.Google Scholar
7. Likharev, K.K, “Riding the crest of a new wave in memory [NOVORAM],” Circuits and Devices Magazine, IEEE, Volume: 16, Issue: 4, July 2000, pp.16–21 Google Scholar
8. Eitan, B.; Pavan, P.; Bloom, I.; Aloni, E.; Frommer, A.; Finzi, D.; “NROM: A novel localized trapping 2-bit nonvolatile memory cell,” Electron Device Letters, IEEE, Volume: 21, Issue: 11, Nov. 2000, pp. 543–545 Google Scholar
9. De Blauwe, J., “Nanocrystal nonvolatile memory devices. Nanotechnology,” IEEE Transactions on, Volume: 1, Issue: 1, March 2002, pp. 72–77 Google Scholar
10. Bauer, M., Alexis, R.; Atwood, G.; Baltar, B.; Fazio, A.; Frary, K.; Hensel, M.; Ishac, M.; Javanifard, J.; Landgraf, M.; Leak, D.; Loe, K.; Mills, D.; Ruby, P.; Rozman, R.; Sweha, S.; Talreja, S.; Wojciechowski, K.; “A Multilevel-Cell 32Mb Flash Memory,” Technical Digest IEEE International Solid State Circuits Conference, 1995, pp. 132, 133.Google Scholar
11. Tehrani, S., Slaughter, J., Deherrera, M., Engel, B., Rizzo, N., Salter, J., Durlam, M., Dave, R., Janesky, J., Butcher, B., Smith, K., Grynkewich, G., “Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions”, Proceedings of the IEEE, Vol. 91, Issue 5, May 2003, pp. 703–714 Google Scholar
12. Moise, T., et. al., “Demonstration of a 4Mb, High Density Ferroelectric Memory Embedded Within a 130nm, 5 LM Cu/FSG Logic Process”, IEDM 2002, International, pp. 535–538 Google Scholar
13. Lai, S., Lowrey, T., “OUM–A 180nm Nonvolatile Memory Cell Element Technology for Stand Alone and Embedded Applications”, IEDM, Digest International, Dec. 2001.Google Scholar
14. Zhuang, W., Pan, W., Ulrich, B., Lee, J., Stecker, L., Burmaster, A., Evans, D., Hsu, S., Tajiri, M., Shimaoka, A., Inoue, K., Naka, T., Awaya, N., Sakiyama, A., Wang, Y., Liu, S., Wu, N., Ignatiev, A., “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, IEDM, Digest International, Dec. 2002, pp. 193–196 Google Scholar
15. Rueckes, T., “Carbon Nanotubes-based Nonvolatile Random Access Memory for Molecular Computing”, Science, 289, 2000, pp. 94 Google Scholar
16. Liu, Z., Yasseri, A., Lindsey, J., Bocian, D., “Molecular Memories That Survive Silicon Device Processing and Real-World Operation”, Science, Vol. 302, Nov. 2003, pp. 1543–1545 Google Scholar
17. Vettiger, P., Cross, G., Despont, M., Drechsler, U., Durig, U., Gotsomann, B., Haberle, W., Lantz, M., Rothuizen, H., Stutz, R., Binnig, G., “The ‘Millipeded’–Nanotechnology Entering Data Storage”, Nanotechnology, IEEE Transactions on, Vol. 1, Issue 1, March 2002, pp. 39–55 Google Scholar
18. Stikeman, A., “Polymer Memory, the plastic path to better storage”, MIT Technology Review, Sept. 2002, pp. 31.Google Scholar
19. “An Introduction to Programmable Metallization Cell Memory Devices” at http://axontc.com Google Scholar