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III-V CMOS technologies on Si platform

Published online by Cambridge University Press:  13 July 2011

M. Takenaka and
S. Takagi
M. Takenaka
Affiliation:
Department of Electrical Engineering and Information Systems, University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
S. Takagi
Affiliation:
Department of Electrical Engineering and Information Systems, University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Abstract

The heterogeneous integration of III-V semiconductors with the Si platform is expected to provide high performance CMOS logic for future technology nodes because of high electron mobility and low electron effective mass in III-V semiconductors. However, there are many technology issues to be addressed for integrating III-V MOSFETs on the Si platform as follow; high-quality MOS interface formation, low resistivity source/drain formation, and high-quality III-V film formation on Si substrates. In this paper, we present several possible solutions for the above critical issues of III-V MOSFETs on the Si platform. In addition, we present the III-V CMOS photonics platform on which III-V MOSFETs and III-V photonics can be monolithically integrated for ultra-large scale electric-optic integrated circuits.

Keywords

III-VSielectrical properties

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1336: Symposium P – Interface Engineering for Post-CMOS Emerging Channel Materials , 2011, mrss11-1336-p05-04
Copyright
Copyright © Materials Research Society 2011

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