Hostname: page-component-7b7567c8c-wxvwp Total loading time: 0 Render date: 2026-11-14T23:21:44.882Z Has data issue: false hasContentIssue false
  • English
  • Français

Impact of Fabrication Process, Layout Variation and Packaging Process on Cu/Low-k Interconnect Reliability

Published online by Cambridge University Press:  01 February 2011

Aditya Karmarkar,
Xiaopeng Xu,
Dipu Pramanik,
Xi-Wei Lin,
Greg Rollins and
Xiao Lin
Aditya Karmarkar
Affiliation:
adityap@synopsys.com, Synopsys (India) Pvt. Ltd., TCAD DFM Solutions, My Home Tycoon, 4th Floor, Block A, Begumpet, Hyderabad, 500016, India, +91-40-40222560, +91-40-23412517
Xiaopeng Xu
Affiliation:
Xiaopeng.Xu@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road,, Mountain View, CA, 94043, United States
Dipu Pramanik
Affiliation:
dpramani@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road,, Mountain View, CA, 94043, United States
Xi-Wei Lin
Affiliation:
Xi-Wei.Lin@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
Greg Rollins
Affiliation:
Greg.Rollins@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
Xiao Lin
Affiliation:
Xiao.Lin@synopsys.com, Synopsys, Inc., TCAD DFM Solutions, 700, East Middlefield Road, Mountain View, CA, 94043, United States
Get access

Abstract

The industry trend towards smaller feature size and higher integration density leads to multi-level Cu/low-k interconnect schemes with reduced line width and spacing. Mechanical stress is generated during interconnect fabrication. The spatial distribution of the stress is strongly affected by the layout variation. The packaging process generates a global chip level stress that permeates to the local interconnect level. Stress related failures and yield loss are major areas of concern for Cu/low-k interconnects. The effects of fabrication process, layout variation, and packaging process on the final stress distributions in Cu/low-k interconnect structures are examined and the reliability impact of mechanical stress is assessed.

Keywords

thermal stressesstructuralmicroelectronics

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

[1] Blaine, J., Kloster, G., et al., Proceedings of the IEEE 2002 International Interconnect Technology Conference, 2002, pp. 242–244.Google Scholar
[2] Cherault, N., Besson, J., et al., Proceedings of 35th European Solid-State Device Research Conference (ESSDERC), 2005, pp. 493–496.Google Scholar
[3] Shen, Y.-L., Proceedings of the 37th Annual IEEE International Reliability Physics Symposium, 1999, pp. 283–290.Google Scholar
[4] Yao, C.H., Huang, T.C., et al., Proceedings of the 2004 IEEE International Interconnect Technology Conference, 2004, pp. 24–26.Google Scholar
[5] Mercado, L.L., Goldberg, C., et al., Proceedings of the 53rd Electronic Components and Technology Conference, 2003, pp. 1784–1790, May 2003.Google Scholar
[6] Fammos-TX Manuals, Synopsys, Inc., March 2007.Google Scholar
[7] Yang, K., Waeterloos, J. J., et al., Proceedings of the 2003 Materials Research Society Symposium, vol. 766, pp. E 6.2.1– E 6.2.6, 2003.Google Scholar
[8] Zhai, C. J., Besser, P. R., et al., Proceedings of the 2004 Materials Research Society Symposium, vol. 812, pp. F1.8.1– F1.8.6, 2004.Google Scholar
[9] Reimbold, G., Sicardy, O., et al., Proceedings of IEEE IEDM 2002, 745 (2002).Google Scholar
[10] Wang, G., Merrill, C., et al., IEEE Transactions on Device and Materials Reliability, vol. 3, no. 4, pp. 119–128, Dec. 2003.Google Scholar