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Integration of Materials and Device Research Enabled by Wafer Bonding and Layer Transfer

Published online by Cambridge University Press:  21 March 2011

Q.-Y. Tong
Q.-Y. Tong*
Affiliation:
Wafer Bonding Lab., Research Triangle Institute and Ziptronix, RTP, NC 27709
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Abstract

Wafer bonding and layer transfer technology has emerged as a versatile approach for integrated research and development of materials and devices. It does not only provide a flexible way to prepare integrated materials but also breaks the barrier between materials science and device engineering since it appears to be one of the fundamental technologies for 3-D device fabrication and for integration of partially or fully processed dissimilar functional layers. The device performance can be significantly enhanced when both sides of device layers can be processed such as in the double gate CMOS and in HBTs. The processed device layers can be considered as unique materials layers and can also be integrated. The integration of dissimilar integrated circuits provides a promising solution to realize micro-systems or system on a 3-D chip in which multi-functional layers are interconnected (3-D SOC). The main issues are to develop methods that form strong bond between required materials at low temperatures and to cut the device layer without compromising the device integrity by using VLSI compatible processes. The advances in low temperature bonding of hydrophilic and hydrophobic silicon, compound semiconductors and other materials in ambient are reviewed, and application examples are discussed.

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References

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