Hostname: page-component-7b7567c8c-2n9c9 Total loading time: 0 Render date: 2026-11-15T14:28:17.956Z Has data issue: false hasContentIssue false
  • English
  • Français

Low Temperature Shallow Junction Formation For 70nm Technology Node And Beyond

Published online by Cambridge University Press:  01 February 2011

John O. Borland
John O. Borland*
Affiliation:
Varian Semiconductor Equipment Associates 4 Stanley Tucker Dr. Newburyport, MA 01950, USA
Get access

Abstract

Low temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 717: Symposium C – Si Front-End Junction Formation Technologies , 2002, C1.1
Copyright
Copyright © Materials Research Society 2002

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

1. Niwa, M., short course presentation material at IEEE 2000 Symposium on VLSI Technology, June 2000.Google Scholar
2. Osburn, C., North Carolina State Univ., presentation material on replacement gate process at ISEMATECH gate stack working group meeting June 2000.Google Scholar
3. Phillip, H. S. Wong, short course presentation material at IEEE IEDM 1999 on sub-100nm CMOS showing TI's replacement gate results, Dec. 1999.Google Scholar
4. 2001 International Technology Roadmap for Semiconductors (www.public.itrs.net).Google Scholar
5. Ghani, T. et al., VLSI Symposium 2000, section 18.1, p.174, June 2000.Google Scholar
6. Osburn, C. et al, Jour. of Vac. Science and Technology, vol.18, Jan-Feb. 2000, p.338.Google Scholar
7. Narasimha, S. et al, IEEE, IEDM-2001, section 29.2, p.625, Dec. 2001.Google Scholar
8. Borland, J., USJ presentation material at the 4th National Implant Users Group Meeting, Austin, Texas, Oct. 18, 2001.Google Scholar
9. Shishiguchi, S. et al., the ECS PV99-10, ECS Conf., May 1999, p.105.Google Scholar
10. Osburn, C., NCSU private communications.Google Scholar
11. Murto, B., presentation material at I-SEMATECH source drain meeting March 2000.Google Scholar
12. Borland, J., Semiconductor International, April 2001, p.70.Google Scholar
13. Kim, S. et al., IEEE, IEDM 2000, section 31.3, p.723, Dec. 2000.Google Scholar
14. Gossmann, H. et al., Material Research Society, vol. 610, Spring MRS Meeting April 2000, p. B1.2.1. Google Scholar
15.VSEA internal results for 500eV implantation.Google Scholar
16. Borland, J., private communications with customers on 70nm & 100nm targets.Google Scholar
17. Bourdelle, K. et. al, IIT-2000, Sept. 2000, p.25, Alpbach, Austria.Google Scholar
18. Jain, A. of TI, discussions at the I-SEMATECH source drain engineering working group meeting Nov.8, 2001.Google Scholar
19. Downey, D. et al, the Electrochemical Society, Spring Meeting May 1999, PV 99-10, p.151.Google Scholar
20. Matsuda, T. et al, extended abstract of the International Workshop on Junction Technology, section 2-3, Dec. 2000, p.29, Chiba, Japan.Google Scholar
21. Jacobson, D. et al, IIT-2000, Sept. 2000, p.300, Alpbach, Austria.Google Scholar
22. Gelpy, J. of Vortek, presentation material at the I-SEMATECH source drain engineering working group meeting Nov.8, 2001.Google Scholar
23. Felch, S. et al, joint VSEA/Verdant patent filing on sub-melt laser annealing, April 2000.Google Scholar
24. Ito, T. et al, extended abstract of the 2001 SSDM conference, section A-5-3, p.182, Sept. 2001.Google Scholar
25. Takamura, Y. et al., Material Research Society, vol. 669, Spring MRS Meeting April 2001, p. J7.3.1. Google Scholar
26. Talwar, S., et al., presentation material on laser melt annealing at the Spring MRS 2001 meeting, April 2001.Google Scholar
27. Osburn, C. et al, IIT-96, p.607, June 1996, Austin, Texas. Google Scholar
28. Jacobson, D., private communications.Google Scholar
29. Borland, J. & Galewski, C., IIT-98, p.1211, June 1998, Kyoto, Japan. Google Scholar
30. Ponmanev, Y. et al., IEEE 2001 Symposium on VLSI Technology, section 4A-1, p33, June 2001.Google Scholar
31. Tsuji, K., et al., IEEE 1999 Symposium on VLSI Technology, section 2-1, June 1999.Google Scholar
32. Kanemoto, K., et al., extended abstract of the 2000 SSDM conference, section A-7-4, Aug. 2000, p. 406.Google Scholar
33. Borland, J. et al., new SPE patent filing Nov. 2001.Google Scholar
34. Al-Bayati, A., et al, IIT-2000, Sept. 2000, p.54, Alpbach, Austria.Google Scholar