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Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation

Published online by Cambridge University Press:  01 February 2011

Aditya P Karmarkar,
Xiaopeng Xu,
Sesh Ramaswami,
John Dukovic,
Kedar Sapre and
Ajay Bhatnagar
Aditya P Karmarkar
Affiliation:
adityap@synopsys.com, Synopsys (India) Private Limited, Hyderabad, India
Xiaopeng Xu
Affiliation:
Xiaopeng.Xu@synopsys.com, Synopsys, Inc., Mountain View, California, United States
Sesh Ramaswami
Affiliation:
Sesh_Ramaswami@amat.com, Applied Materials, Inc., Santa Clara, California, United States
John Dukovic
Affiliation:
John_Dukovic@amat.com, Applied Materials, Inc., Santa Clara, California, United States
Kedar Sapre
Affiliation:
Kedar_Sapre@amat.com, Applied Materials, Inc., Santa Clara, California, United States
Ajay Bhatnagar
Affiliation:
Ajay_Bhatnagar@amat.com, Applied Materials, Inc., Santa Clara, California, United States
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Abstract

Through-silicon via (TSV) structures with various material and geometry configurations are assessed to study their impact on reliability, isolation and performance. Oxide liner insulators show a larger performance impact as compared to low-k liners and the effect decreases with increasing liner insulator thickness. Higher density of the TSV array causes greater stress impact on carrier mobility and increases the parasitic capacitance. Additionally, low-k liner reduces the parasitic capacitance, but exhibits lower strength and adhesion, therefore degraded reliability. These results provide an important perspective of performance and reliability trade-offs necessary for a robust TSV design.

Keywords

insulatordielectric propertiesthermal stresses

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