Hostname: page-component-6898cfcb55-zsp5v Total loading time: 0 Render date: 2026-11-11T12:27:17.583Z Has data issue: false hasContentIssue false
  • English
  • Français

A Multilayer Interconnect Process for 0.5um Logic Technology

Published online by Cambridge University Press:  25 February 2011

Donghyun Kim,
H.S. Oh,
K.Y. Lee,
Y.S. Kim,
B.S. Kim and
B.G. Kim
Donghyun Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
H.S. Oh
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
K.Y. Lee
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
Y.S. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
B.S. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
B.G. Kim
Affiliation:
Basic Technology Center, Samsung Electronics Co., Kihung, Republic of Korea.
Get access

Abstract

A submicron triple metal process for 0.5um logic CMOS is described, focusing on key process steps such as the dielectric planarization and metallization. The main emphasis has been placed on development of ar complicated planarization process utilizing SOG (Spin on Glass) etchback. In this paper, we report process data of triple metal technology which uses aluminum alloy for interconnects and P-TEOS (Plasma Tetra Ethyl Ortho Silicate) with siloxane SOG and etchback process for planarization.

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

1 SHORT COURSE: INTERCONNECT FOR THE ‘90S. ANS/9-92, IEDM, (1992)Google Scholar
2 Ting, C.H., Lin, H.Y. and Pai, P.L., Oldham, W.G., Planarization process using Spin-On -Glass; Process considerations for using Spin-On-Glass as a planarizing Dielectric Film, Proc. VLSI Multilevel Interconnection Conf., Junel.15- 16 (1987).Google Scholar
3 Kojima, H., Iwamori, T., Sakata, Y., Yamashita, T. and Yatsuda, Y., Planarization process using a multi-coating of Spin-On-Glass, Proc. VLSI Multilevel Interconnection Conf., Junel3-(1988).Google Scholar
4 Akira, Hashimoto, Materials to cope with semiconductors in the following generation, Tokyo Ohka Kogyo Co., Ltd., Semicon NEWS (Jul. 1988)Google Scholar
5 Wolf, , Silicon Processing for the VLSI Era, Volume2-Process Integration (LATTICE PRESS, Sunset Beach, California 90742. 1990)Google Scholar
6 Hirasita, N., Kobaykawa, M., Armatsu, A., Yokayama, F. and Ajioka, T.: J, Electrochem. Soc.vol. 139, p794,1992 CrossRefGoogle Scholar
7 Ohiwa, T., Horika, K., Arikado, T., Hasegawa, I. and Okao, H.: Proc. of 12th Symp. on Dry Process (IEE of Japan, pl05, 1990.Google Scholar