Hostname: page-component-7b7567c8c-7pwfn Total loading time: 0 Render date: 2026-11-13T17:03:46.098Z Has data issue: false hasContentIssue false
  • English
  • Français

Novel Stacked CMOS Process by Local Overgrowth

Published online by Cambridge University Press:  21 February 2011

René P. Zingg,
B. Hüfflinger and
G. W. Neudeck
René P. Zingg
Affiliation:
Institute for Microelectronics, Allmandring 30a, D-7000 Stuttgart 80, FRG; Tel: 0049-711-685-5777, FAX: 0049-711-685-5930
B. Hüfflinger
Affiliation:
Institute for Microelectronics, Allmandring 30a, D-7000 Stuttgart 80, FRG; Tel: 0049-711-685-5777, FAX: 0049-711-685-5930
G. W. Neudeck
Affiliation:
Purdue University, Dept. of El. Engineering, West Lafayette, IN 47907, USA
Get access

Abstract

A six mask process that yields stacked CMOS circuits is presented. Transistors that were built in reverse order (i. e. the gate first, the gate dielectric second, and only then the channel region) exhibit comparable parameters as conventional devices. A novel device has been built whose current drive is three times that of FETs built in substrate material. The vertical stacking of complementary MOS transistors made it possible to build an inverter with symmetric switching characteristic within the area of a single transistor.

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

[1] Akasaka, Y., “Three-Dimensional IC Trends”, Proc. of the IEEE 74 (12), pp 1703–1714, December 1986 Google Scholar
[2] Höfflinger, B., Liu, S. T. and Vajdic, B., “A Three-Dimensional CMOS Design Methodology”, IEEE SC–19 (1), pp37–39, February 1984 Google Scholar
[3] Gibbons, J. F. and Lee, K. F., “One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon”, IEEE EDL–3 (8), pp 117–118, June 1980 Google Scholar
[4] Zingg, R. P., Neudeck, G. W., Höfflinger, B. and Liu, S. T., “Epitaxial Lateral Overgrowth of Silicon over Steps of Thick Si02” J. of the El-chem. Soc, Vol 133 (6), pp1274–1275, June 1986 Google Scholar
[5] Hoffmann, K., Rubloff, G. W. and McCorkle, R. A., “Defect formation in thermal Si02 by high-temperature annealing”, Appl. Phys. Lett, 49 (22), pp1525–1527, December 1986 Google Scholar
[6] Zingg, R. P., Graf, H. G., Appel, W., Vöh-ringer, P. and Höfflinger, B., “Thinning Techniques for 1μm ELO-SOI”, IEEE SOS/SOI Workshop Proc. p. 52, October 1988 Google Scholar
[7] Faraone, L. and Harbeke, G., “Surface Roughness and Electrical Conduction of Oxide/Polysilicon Interfaces”, J. of the El-chem. Soc, Vol 133 (7), pp1410–1413, July 1986 Google Scholar
[8] Colinge, J. P., Demoulin, E. and Lobet, M., “Stacked Transistor CMOS (ST-CMOS), an NMOS Technology Modified to CMOS”, IEEE SC–17 (2), pp215–219, April 1982 Google Scholar
[9] Zingg, R. P., Höfflinger, B. and Neudeck, G. W., “High Quality Dual-Gate PMOS Devices in Local Overgrowth (LOG)”, IEE EL–25 (15), pp1009–1011, July 20, 1989 Google Scholar
[10] Friedrich, J. A. and Neudeck, G. W., “Interface Characterization of Silicon Epitaxial Lateral Growth over Existing SiO2 for Three-Dimensional CMOS Structures”, IEEEE DL–10 (4), pp144–146, April 1989 Google Scholar
[11] Barth, P. W., Apte, P. R. and Angell, J. B., “The MISIM-FET in Thin Semiconductor Layers: Depletion-Approximation Model of I-V Characteristics”, IEEE ED–30 (12), pp 1717–1726, December 1983 Google Scholar
[12] Lim, H. K. and Fossum, J. G., “Current-Voltage Characteristics of Thin-Film SOI MOSFET's in Strong Inversion”, IEEE ED–31 (4), pp401–408, April 1984 Google Scholar
[13] Lim, H. K. and Fossum, J. G., “Threshold Voltage of Thin-Film Silicon-on-Insulator (SOI) MOSFET's”, IEEE ED–30 (10), pp1244–1251, October 1983 Google Scholar
[14] Sekigawa, T. and Hayashi, Y., “Calculated Threshold-Voltage Characteristics of an XMOS Transistor Having an Additional Bottom Gate”, Sol. State Electronics Vol. 27 (8/9) pp827–828, 1984 Google Scholar
[15] Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J. and Elawa, T., “Double-Gate Silicon-on-Insulator Transistor with Volume Inversion: A New Device with Greatly Enhanced Performance”, IEEE EDL–8 (9), pp410–412, September 1987 Google Scholar
[16] Zingg, R. P., Höfflinger, B. and Neudeck, G. W., “Stacked CMOS Inverter with Symmetric Device Performance”, IEDM Meeting, Washington, DC, December, 1989 Google Scholar