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Probing the Limits of Silicon-Based Nanoelectronics

Published online by Cambridge University Press:  15 February 2011

S. J. Wind,
Y. Taur,
Y. Mii,
D. J. Frank,
H.-S. Wong,
D. A. Buchanan,
S. A. Rishton,
J. J. Bucchignano,
Y. Lii and
K. A. Jenkins
S. J. Wind
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
Y. Taur
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
Y. Mii
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
D. J. Frank
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
H.-S. Wong
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
D. A. Buchanan
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
S. A. Rishton
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
J. J. Bucchignano
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
Y. Lii
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
K. A. Jenkins
Affiliation:
IBM T.J. Watson Research Center P.O. Box 218 Yorktown Heights, NY 10598
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Abstract

The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.

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References

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