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Reliability Issues with Mixed-Signal CMOS Technology

Published online by Cambridge University Press:  15 February 2011

Rajeeva Lahri,
Hung-Sheng Chen,
Ji Zhao,
Kamesh Gadepally and
C.S. Teng
Rajeeva Lahri
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Hung-Sheng Chen
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Ji Zhao
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
Kamesh Gadepally
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
C.S. Teng
Affiliation:
CMOS Technology Development, National Semiconductor Corp, Santa Clara, CA 95052
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Abstract

In a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 391: Symposium T – Materials Reliability in Microelectronics V , 1995, 47
Copyright
Copyright © Materials Research Society 1995

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