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SiGeC Cantilever Micro Cooler

Published online by Cambridge University Press:  01 February 2011

Gehong Zeng,
Ali Shakouri,
Edward Croke,
Yan Zhang,
James Christofferson and
John E. Bowers
Gehong Zeng
Affiliation:
Department of Electrical and Computer Engineering, University of California Santa Barbara, CA 93106
Ali Shakouri
Affiliation:
Baskin School of Engineering, University of California, Santa Cruz, CA 95064
Edward Croke
Affiliation:
HRL Laboratories, LLC, Malibu, California, 90265
Yan Zhang
Affiliation:
Baskin School of Engineering, University of California, Santa Cruz, CA 95064
James Christofferson
Affiliation:
Baskin School of Engineering, University of California, Santa Cruz, CA 95064
John E. Bowers
Affiliation:
Department of Electrical and Computer Engineering, University of California Santa Barbara, CA 93106
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Abstract

The fabrication and characterization of SiGeC cantilever microcoolers are described. Silicon on insulator (SOI) was used as the substrate, and two layers of 3 μm p-SiGe0.07C0.0075 and 1.14 μm n-SiGe0.07C0.0075 lattice matched to silicon were grown using molecular beam epitaxy. The uni couple cooler was fabricated using conventional integrated circuit (IC) processing, and the cantilever structure was finally formed by removing the backside Si of SOI substrate by deep reactive ion etching. Devices with different n- and p-side length ratios were characterized. Cooling by 1.2K has been measured at room temperature. Modeling showed that the device performance was dominated by the smaller cooling temperature of the p-SiGeC leg of the cantilever structure. Parasitic heat conduction through the Si buffer layer is the main limitation to the device performance.

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References

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