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Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages

Published online by Cambridge University Press:  31 January 2011

Aditya Karmarkar,
Charlie Zhai,
Xiaopeng Xu,
Xiao Lin,
Greg Rollins and
Victor Moroz
Aditya Karmarkar
Affiliation:
AdityaP.Karmarkar@synopsys.com, Synopsys (India) Private Limited, Hyderabad, India
Charlie Zhai
Affiliation:
czhai@nvidia.com, Nvidia, Silicon Operations, Santa Clara, California, United States
Xiaopeng Xu
Affiliation:
Xiaopeng.Xu@synopsys.com, Synopsys, Inc., TCAD, Mountain View, California, United States
Xiao Lin
Affiliation:
Xiao.Lin@synopsys.com, Synopsys, Inc., TCAD, Mountain View, California, United States
Greg Rollins
Affiliation:
Greg.Rollins@synopsys.com, Synopsys, Inc., TCAD, Mountain View, California, United States
Victor Moroz
Affiliation:
Victor.Moroz@synopsys.com, Synopsys, Inc., TCAD, Mountain View, California, United States
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Abstract

Viscoelastic stress relaxation occurs at operating temperature in underfill materials of flip-chip packages with high power devices. Multi-level finite element analysis is performed to study the impact of the viscoelastic relaxation on package reliability. The stress simulations reveal that the relaxation in underfill material leads to higher stress concentration in solder bumps. The failure analysis shows that the induced high stress develops higher crack driving forces. The results demonstrate that the underfill material property such as viscosity can shift failure mode from die corner delamination to near bump delamination. Therefore, the numerical study can be used as a guideline to select underfill material for package reliability improvements.

Keywords

packagingviscoelasticitythermal stresses

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