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The ANSTO Isotope Cycling System

Published online by Cambridge University Press:  09 February 2016

G C Watt*
Affiliation:
Australian Nuclear Science and Technology Organisation, Lucas Heights 2234, NSW, Australia
S Boronkay
Affiliation:
Balaton Technologies, PO Box 368, Rose Bay 2029, NSW, Australia
A M Smith
Affiliation:
Australian Nuclear Science and Technology Organisation, Lucas Heights 2234, NSW, Australia
M A C Hotchkis
Affiliation:
Australian Nuclear Science and Technology Organisation, Lucas Heights 2234, NSW, Australia
*
2 Corresponding author. Email: gwx@ansto.gov.au.
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Abstract

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A number of electronic systems are used on the ANTARES accelerator at ANSTO to implement its fast cycling accelerator mass spectrometry (AMS) capability. The fast cycling system was originally installed and commissioned in 1993 and has recently been updated. This paper describes the more significant of the electronic systems, such as the controller (“sequencer”), the high-voltage power supply (“bouncer”), the fast electrostatic beam chopper, and those used for measurement of the pulsed ion beam current. The sequencer, a programmable 15-bit digital pulse generator, generates the timing and sequencing of the control signals for bouncing voltage selection, beam chopping, Faraday cup current measurement, and rare isotope event measurement. The new sequencer is implemented using a National Instruments FPGA (field programmable gate array) card, programmed using LabVIEW 2010. This device has the benefits of host CPU-independent operation, simple interfacing (PCI), a small footprint, off-the-shelf availability at modest cost, and ease of functionality upgrade. The sequencer provides 15 synchronous digital signals, whose “on” and “off” transitions can be independently specified, in both number and time, with a time resolution of between 0.5 and 128 μs, and with the total duration between repetitions adjustable between 65.5 ms and 8.4 s per cycle. It is hosted by a generic PC because of the low-cost and ubiquity of these. The stand-alone FPGA-based approach ensures that the sequencer determinism is unaffected by processes executing in the host CPU.

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