UWB LNA MMIC circuit topology and design

The proposed UWB LNA MMIC design is implemented using the 0.15 µm GaAs pHEMT technology of Sanan Semiconductor. In order to balance the size, power consumption, and gain of the chip, a current-reuse topology is adopted, where the two transistors M₁ and M₂ have the same size, which is 4 × 45 µm. Based on this, the proposed LNA schematic is presented in Fig. 1, which includes two NFNs, a source adaptive bias circuit, and a current-reuse construction. All parameter values in the circuit are given as shown in Table 1.

Figure 1.

Circuit schematic of the proposed UWB LNA MMIC.

Table 1.

Parameters of the proposed UWBLNA MMIC (UNIT: L, nH; R, Ohm; C, pF; TRANSMISSION LINE-W/L, µm/µm; M, µm²)

Para: Parameter.

As demonstrated in Fig. 1, the transmission path guided by the red dashed line with the drain current I _d is the direct-current (dc) path of the proposed LNA. The circuit located in the orange shaded area is the current-reuse construction used, where transistors M₁ and M₂ share the same drain supply, which can effectively reduce the power loss of LNA MMIC. The transmission path guided by the blue dotted line with the radio frequency (RF) mark is the RF path of the proposed LNA, in which the inductor L ₂ is used to prevent the RF signal from leaking into the dc path, and similarly, the capacitor C₇ is used to prevent the dc signal from entering the RF path.

The gate bias voltage (−0.5 V) of the first stage is generated by the drain current of transistor M₂ acting on the resistor R₇ in the adaptive bias network, which can eliminate the design of the gate bias network of transistor M₁, weaken the design complexity of the dc power supply network, and help reduce the overall size of the chip. In addition, the adaptive bias network RC located at the source of transistor M₁ combined with microstrip line T₂ can form source stage feedback to achieve bandwidth expansion, specifically manifested in the capacitive reactance decreases with increasing frequency, which helps to compensate for the inherent gain roll-off of the transistor [Reference Razavi16]. The gate bias voltage of the second stage transistor M₂ is provided by a resistive voltage divider network composed of R₅ and R₆, which also helps to reduce the design complexity of the dc power supply network. In addition, the resistor voltage divider network composed of R₅ and R₆ is also used to promote the OP_1 dB of LNA, which is mainly achieved by manipulating the drain source voltage (V_ds1 and V_ds2) distribution of transistors M₁ and M₂ using the ratio of R₅ and R₆. For this design, the OP_1 dB of LNA is determined by the second stage transistor M₂, while for the current-reused structure, the drain current (I _ds) of the two stage transistors is the same. Therefore, increasing the output power of the second stage can be achieved by increasing the drain source voltage V_ds2 of M₂.

Moreover, in order to compensate for the inherent gain roll-off characteristics of transistors, feedback techniques are also introduced into the proposed LNA MMIC circuit design. As a result, a NFN composed of R-L-C is employed in the two stages of the proposed LNA to achieve bandwidth expansion, as exhibited in Fig. 1. Figure 2 demonstrates the simulated gain curves with and without NFNs for the proposed LNA MMIC, where C₃ and C₅ are used to isolate dc from the gate and drain stages of transistors M₁ and M₂. As displayed in the simulation results in Fig. 2, it can be seen that the LNA MMIC without the addition of NFN exhibits a more obvious gain roll-off characteristic. Compared to introducing feedback circuit only in the first or second stage, the bandwidth expansion effect generated by introducing R-L-C NFN in both stages of amplification topology is more obvious through compensating for the gain roll-off of the transistor.

Figure 2.

Simulated gain curves with and without NFNs for the proposed LNA MMIC.

To verify the conversion performance of the input impedance and output impedance to 50Ω completed by the input matching network of the first stage and the output matching network of the second stage of the topology network presented in Fig. 1, the simulated impedance trajectories of the input and output terminals of the proposed LNA MMIC are plotted in Fig. 3, where the orange solid line represents the input terminal and the green dashed line represents the output terminal. As exhibited in the figure, the impedance completed at both the input and output terminals varies closely around the 50Ω at the center of the Smith chart, indicating the rationality of the matching network design.

Figure 3.

The simulated impedance trajectory variation of the input and output of the proposed LNA MMIC in 2–18 GHz.

Simulated and measured results

As a validation of the proposed design method, a prototype is designed, fabricated, and measured using a 0.15-µm GaAs pHEMT process. Figure 4 demonstrates a photograph of the proposed UWB LNA MMIC with a chip area of 1.2 × 1.5 mm². The measured LNA consumes a 44-mA dc current from a 5-V dc supply, which generates a 220-mW dc consumption.

Figure 4.

Chip microphotograph of the proposed UWB LNA.

Subsequently, the small signal measurement is executed, and the measured results for the S-parameter are plotted in Fig. 5(a). As displayed in the figure, it can be seen that within the target frequency band of 2–18 GHz, the proposed LNA MMIC achieves S₂₁ between 15.5 and 17.8 dB, while S₁₁ and S₂₂ are maintained below −16.3 and −14.5 dB, respectively. Furthermore, the voltage-standing-wave ratio (VSWR) at the input of the measured LNA MMIC is presented in Fig. 5(b). As exhibited in the figure, the implemented VSWR is between 1.127 and 1.35 in the entire S-C-X-Ku-band. Meanwhile, Fig. 5(c) demonstrates that the measured OP_1 dB is 15 ± 0.5 dBm for V _D = 5 V over the 2–18 GHz.

Figure 5.

Simulated and measured results of small-signal. (a) S-parameter. (b) VSWR. (c) OP_1 dB.

The NF measurement of the fabricated LNA MMIC is performed, and the simulated and tested results are exhibited in Fig. 6, where the measured NF is between 3 and 3.65 dB from 2 to 18 GHz. It should be noted that the lack of outstanding NF performance of the proposed LNA is mainly attributed to two aspects. First, in the target frequency band of 2–18 GHz, in order to balance the NF performance in the high-frequency band, it is necessary to sacrifice the noise performance in the low-frequency band to ensure that the NF of the entire design frequency band is at an acceptable level. The second is that 1/f noise within the entire design frequency band can also have a significant impact on the NF of LNA.

Figure 6.

Measured result of NF from 2–18 GHz.

Besides, the measured the input third-order intercept point (IIP3) of LNA in the target frequency band range of 2–18 GHz using a two-tone signal with an interval of 1 MHz and an input power of 5 dBm, is shown in the Fig. 7. It can be seen that within the target frequency band, the proposed LNA MMIC achieves IIP3 between 9.8 and 11.6 dBm.

Figure 7.

Measured IIP3 of the designed amplifier against frequency.

Based on reference [Reference Zhang, Wang, Yan and Liang21], a modified figure of merit (FOM) considering the center frequency, bandwidth, gain, NF, dc power, and OP_1 dB, is adopted to conduct a state-of-the-art comparison as follows [Reference Zhang, Wang, Yan and Liang21]:

(1)\begin{align}FOM = 20\log {}_{10}\left( {\frac{{Gain\left[ {abs} \right] \cdot O{P_{1dB}}\left[ {mW} \right]}}{{\left( {N{F_{\min }}\left[ {abs} \right] - 1} \right) \cdot {P_{dc}}\left[ {mW} \right]}} \cdot \frac{{BW\left[ {GHz} \right]}}{{{f_0}\left[ {GHz} \right]}}} \right)\nonumber\\ \end{align}

where f ₀ is the center frequency. As a result, a comparison between the proposed LNA MMIC and other published LNA MMICs is presented in Table 2. By comparing the performance parameters in the table, it can be concluded that the implemented LNA demonstrates a comprehensive technical advantage.

Table 2.

Comparisons with state-of-the-art integrated LNA MMIC

# Estimated value from the figure.