A) Buck converter

The majority of designs uses a pulse-width modulation (PWM) generator in conjunction with a proportional–integral–derivative (PID) controller to control the converter power switches [Reference Mihajlovic, Lehman and Sun7, Reference Pinon, Allard and Garnier8]. The behavior of this approach can be easily characterized by the means of linear control theory. The switching frequency is defined exactly through the fixed period of the PWM signal. But an implementation with a very high bandwidth is difficult due to the complexity of the individual components. Hence, the straightforward and robust sliding mode like control approach shown in Fig. 2 is applied. Its dynamic behavior is characterized by the following nonlinear delayed differential equation (DDE):

(1)$${\dot x}\lpar t\rpar =\left\{{\matrix{ {A_ - x\lpar t\rpar +b_ - } \hfill & {{\rm for}\; V_{S} \lpar t - \Delta t\rpar +\displaystyle{{\tau I_L } \over C}\lt c^T x\lpar t - \Delta t\rpar }\comma \hfill \cr {A_+x\lpar t\rpar +b_+} \hfill & {{\rm otherwise.}} \hfill}}\right.$$

Fig. 2.

Model of the proposed buck converter control architecture.

The vector $x = \left({\matrix{ V & I \cr } } \right)^T $ denotes the state of the system and consists of the voltage across the capacitor C and the current through the inductor L. The matrices A _{−, +} and the vectors b _+,− and c were introduced to present the DDE and also the following equations in a compact form. They are defined as follows:

(2)$$\matrix{A_{ -\comma +} = \left({\matrix{ { - \displaystyle{1 \over {CR_L }}} & {\displaystyle{1 \over C}} \cr { - \displaystyle{1 \over L}} & { - \displaystyle{{R_{ -\comma +} } \over L}} \cr } } \right)\comma \quad b_{-} = \left({\matrix{ { - \displaystyle{{I_L } \over C}} & 0 \cr } } \right)^T \comma \hfill \cr b_ +=\left({\matrix{ { - \displaystyle{{I_L } \over C}} & {\displaystyle{{V_{DD} } \over L}} \cr } } \right)^T \comma \quad c=\left({\matrix{ {1 - \displaystyle{\tau \over {CR_L }}} & {\displaystyle{\tau \over C}} \cr } } \right)^T. } \eqno\lpar 2\rpar$$

For a fixed setting of the power switches S an inhomogeneous differential equation describes the propagation of the state vector x. Hence, it is possible to introduce an affine transformation

(3)$$\eqalignno{&{\cal T}_{\Delta t}^\sigma x = {\it e}^{A_{\sigma} \Delta t} \left(x\lpar t\rpar - x_\sigma \right)+ x_\sigma = x\lpar t + \Delta t\rpar \comma \; \cr & \quad \sigma \in \left\{-\comma \; + \right\}\comma \;}$$

which evaluates the propagation of the space of all state vectors (phase space) for a given time t and the setting σ of S. As A _σ is a 2 × 2 matrix, the exponential matrix used in this equation can be calculated in the following way:

(4)$${e}^{A_\sigma t}={e}^{ - \delta _\sigma t} \left[{1\cos \; \Omega _\sigma t+\displaystyle{{A_\sigma+1\delta _\sigma } \over {\Omega _\sigma }}\sin \; \Omega_\sigma t} \right].\eqno\lpar 4\rpar$$

The variable δ_σ denotes the real part and Ω_σ the positive imaginary part of the two conjugate complex eigenvalues of A _σ

(5)$$\delta_\sigma = \displaystyle{1 \over {2CR_L}} + \displaystyle{{R_\sigma } \over {2L}}\comma \; \quad {\Omega _\sigma} = \sqrt {\displaystyle{1 \over {LC}} \left({1 + \displaystyle{{R_\sigma } \over {R_L }}} \right)- \delta _\sigma ^2 } .\eqno\lpar 5\rpar$$

The stationary state for each setting of the power switches is characterized by the vectors

(6)$$x_ -=\displaystyle{1 \over {R_L+R_ - }}\left({\matrix{ { - I_{L} R_ - R_{L}} \cr {I_{L} R_{L} } \cr } } \right)\comma \; \eqno\lpar 6\rpar$$

(7)$$x_ +=\displaystyle{1 \over {R_L+R_+}}\left({\matrix{ {\left[{V_{{DD}} - I_{L} R_+} \right]R_{L}} \cr {V_{{DD}}+I_{L} R_{L} } \cr } } \right).\eqno\lpar 7\rpar$$

Assuming that the input signal V _S is continuous, the points in time t _K when S are changing their state are specified by the following transcendental nonlinear system of two equations:

(8)$$\eqalign{&\matrix{ {V_{S} \lpar t_{2k+1} - {\Delta }t\rpar +\displaystyle{{\tau I_L } \over C}=} {c^T {{\cal T}}_{{\Delta }t_{2k} - {\Delta }t}^ - x_{2k}\comma \; }\cr& \hfill \cr {V_{S} \lpar t_{2k+2} - {\Delta }t\rpar +\displaystyle{{\tau I_L } \over C}=} {c^T {{\cal T}}_{{\Delta }t_{2k+1} - {\Delta }t}^+x_{2k+1}}\comma \; \hfill \cr } \cr&{\rm with}\; {\Delta }t_k=t_{k+1} - t_k \; {\rm and}\; x_k=x\lpar t_k \rpar .}\eqno\lpar 8\rpar$$

If there exists more than one solution for t _2k or t _2k+1, the smallest positive one has to be used for further considerations. With the set of n points in time t _k and an initial condition x(t ₀) the state of the model is determined for all times t ₀ < t < t _n by a recursive equation as follows:

(9)$$x\lpar t\rpar = \left\{{\matrix{ {{\rm {\cal T}}_{t - t_{2k} }^ - x_{2k} } \hfill & {{\rm for}\; t_{2k} \leq t \leq t_{2k+1} }\comma \; \hfill \cr {{\rm {\cal T}}_{t - t_{2k+1} }^+x_{2k+1} } \hfill & {{\rm for}\; t_{2k+1}\lt t\lt t_{2k+2}. } \hfill \cr } } \right.\eqno\lpar 9\rpar$$

The system (8) is well suited for numerical evaluation but it does not have an analytical solution. To overcome this problem it is linearized. This leads to the following analytical approximations for the points in time when S changes its state:

(10)$$t_{2k+1} = \displaystyle{{c^T \left({{\rm {\cal T}}_{ - \Delta t}^+- {\rm {\cal T}}_{ - \Delta t}^ - } \right)x_{2k} } \over {c^T e^{ - A_ - \Delta t} \left({A_ - x_{2k}+b_ - } \right)- \dot V_{S2k} }}+t_{2k}\comma \; \eqno\lpar 10\rpar$$

(11)$$t_{2k+2}=\displaystyle{{c^T \left({{\rm {\cal T}}_{ - \Delta t}^+- {\rm {\cal T}}_{ - \Delta t}^ - } \right)x_{2k+1} } \over { - c^T e^{ - A_+\Delta t} \left({A_+x_{2k+1}+b_+} \right)+\dot V_{S2k} }}+t_{2k+1} .\eqno\lpar 11\rpar$$

Now, two important parameters of the buck converter, the switching frequency

(12)$$f_{2k}=\displaystyle{1 \over {t_{2k+2} - t_{2k} }}\eqno\lpar 12\rpar$$

and the duty cycle

(13)$$d_{2k}=\left({t_{2k+2} - t_{2k+1} } \right)f_{2k}\eqno\lpar 13\rpar$$

at the output of the power switches can be calculated. Ideally, the output voltage V of the DC–DC converter follows exactly the control signal V _E of the envelope detector. Due to the delay Δt of the comparator such behavior is impossible. The best case, which can be achieved, is described by the following equation:

(14)$$V_{2k+2}=V_{{E}2k}+\displaystyle{{\dot V_{E2k} } \over {f_{2k} }}\; {\rm with}\; V_{{E}/Sk}=V_{{E}/{S}} \lpar t_k - {\Delta }t\rpar .\eqno\lpar 14\rpar$$

A linear approximation of the output voltage propagation at the duty cycle d allows the matching between the present and the desired behavior,

(15)$$V_{2k+2} = e_V^T {\rm {\cal T}}_{\Delta t_{2k+1} }^+{\rm {\cal T}}_{\Delta t_{2k} }^ - x_{2k} \quad \quad {\rm with}\; e_V^T=\left({\matrix{ 1 & 0 \cr } } \right)\eqno\lpar15\rpar$$

(16)$$\hskip 23.5pt= V_{2k}+\displaystyle{{V_{2k}+\alpha _d V_{S2k}+\gamma _d+{\rm {\cal O}}\lpar d_{2k} - d\rpar } \over {\beta _d f_{2k} }}.\eqno\lpar16\rpar$$

The method of equating coefficients applied on the last two equations results in the function

(17)$$V_{S} = \alpha _d V_{E} + \beta _d \dot V_{E} + \gamma _d\eqno\lpar17\rpar$$

which can be used to correct the dynamic behavior of the proposed buck converter. Its coefficients α_d, β_d, and γ_d are calculated as follows:

(18)$$\beta _d = \left({\mathop \sum \limits_\sigma W_\sigma \lpar d\rpar \displaystyle{{\Delta t\tau _\sigma \exp{ - \delta _\sigma \Delta t} } \over {\left({\tau - \tau _\sigma } \right){\rm sinc}\; \Omega _\sigma \Delta t}}} \right)^{ - 1} \; \eqno\lpar18\rpar$$

with $\displaystyle{\rm sinc}={\sin(x)\over x}$

(19)$$\alpha _d = \beta _d \mathop \sum \limits_\sigma W_\sigma \lpar d\rpar \displaystyle{{1 - 2\delta _\sigma \tau _\sigma+\left({\displaystyle{{R_\sigma } \over {R_L }}+1} \right)\omega _0^2 \tau \tau _\sigma } \over {\tau - \tau _\sigma }}\comma \; \eqno\lpar19\rpar$$

(20)$$\gamma _d = \displaystyle{{I_L } \over C}\left({\beta _d - \tau } \right)- e_V^T \left({\alpha _d E+\beta _d A} \right)\mathop \sum \limits_\sigma W_\sigma \lpar d\rpar {\rm {\cal T}}_{\Delta t}^\sigma 0\eqno\lpar20\rpar$$

$${\rm with}\; \quad W_\sigma \lpar d\rpar = \left\{{\matrix{ d \hfill & {{\rm for}\; \sigma = -\comma \; } \hfill \cr {1 - d} \hfill & {{\rm for}\; \sigma = +. } \hfill \cr } } \right.$$

The function β_d (τ) has two simple zeros at τ₋ and τ₊, which are given by the following equation:

(21)$$\tau _\sigma = \displaystyle{1 \over {\Omega _\sigma \cot\; \Omega _\sigma \Delta t+\delta _\sigma }}.\eqno\lpar21\rpar$$

These zeros have a major influence on the stability of the proposed control approach. The system becomes instable if

(22)$$\tau \leq \max {\rm \; }\left\{{\tau _+\comma \; \tau _ - } \right\}=\tau _{Crit}.\eqno\lpar22\rpar$$

With the help of (17) the desired behavior (14) is only achieved, if the linear approximation is valid. As significant evidence the time differences t _Δ2k and t _Δ2k+1 have to be positive. This condition results in two inequalities

(23)$$\dot V_{S2k}\gt c^T e^{ - A_ - \Delta t} \left({A_ - x_{2k}+b_ - } \right)\comma \; \eqno\lpar23\rpar$$

(24)$$\dot V_{S2k}\lt c^T e^{ - A_+\Delta t} \left({A_+x_{2k+1}+b_+} \right).\eqno\lpar24\rpar$$

One major goal during the design of the buck converter is to ensure their compliance for nearly all states of operation.

The energy loss in the power switches of the DC–DC converter during the time t with the initial state x and the switch state σ is denoted by

(25)$${\rm {\cal L}}_t^\sigma x = R_\sigma \mathop \vint \nolimits_0^t \left({{\rm {\cal T}}_{t^{\rm ^{\prime}} }^\sigma x} \right)^T \left({\matrix{ 0 & 0 \cr 0 & 1 \cr } } \right){\rm {\cal T}}_{t^{\rm ^{\prime}} }^\sigma x\, d{\rm t}^{\rm ^{\prime}}.\eqno\lpar25\rpar$$

The used output energy is described in the same way

(26)$${\rm {\cal U}}_t^\sigma x = \mathop \vint \nolimits_0^t \left[{\left({{\rm {\cal T}}_{t^{\rm ^{\prime}} }^\sigma x} \right)^T \displaystyle{1 \over {R_L }}\left({\matrix{ 1 & 0 \cr 0 & 0 \cr } } \right){\rm {\cal T}}_{t^{\rm ^{\prime}} }^\sigma x + I_{L} \left({\matrix{ 1 & 0 \cr } } \right){\rm {\cal T}}_{t^{\rm ^{\prime}} }^\sigma x} \right]\, d{\rm t}^{\rm ^{\prime}}.\eqno\lpar26\rpar$$

The lost/used power of the buck converter during one switch cycle (time interval [t _2k+2, t _2k]) is calculated as follows:

(27)$$P_{L} \lpar x_{2k} \rpar = \left({{\rm {\cal L}}_{\Delta t_{2k+1} }^+x_{2k+1}+{\rm {\cal L}}_{\Delta t_{2k} }^ - x_{2k}+E_{{SW}} } \right)f_{2k}\comma \; \eqno\lpar27\rpar$$

(28)$$P_{U} \lpar x_{2k}\rpar = \left({{\rm {\cal U}}_{\Delta t_{2k+1} }^+x_{2k+1}+{\rm {\cal U}}_{\Delta t_{2k} }^ - x_{2k} } \right)f_{2k}.\eqno\lpar28\rpar$$

The constant E_SW denotes the dynamic energy loss in the power switches during this switch cycle.

B) Statistical description of the envelope

The envelope of the PA RF input signal changes on two time scales: the first one is caused by the modulation and the second one by the power control of the mobile terminal. Both have to be taken into account to get an accurate description of the statistical properties of the envelope signal, which is proportional to the input voltage V_E of the buck converter. For the sake of a compact description the envelope signal is normalized

(29)$$h\lpar t\rpar = \displaystyle{{\hat V_I \lpar t\rpar } \over {\sqrt {2R_0 \bar{P}_I } }}\comma \; \quad \quad \bar {P}_{I/O} = \displaystyle{1 \over {R_0 T_P }} \mathop \vint \nolimits_{t_0}^{t_0+T_{P}} V_{I/O}^2 \lpar t\rpar \, dt.\eqno\lpar29\rpar$$

The constant R ₀ denotes the input resistance of the PA and T _P is the typical time between the change of the output power through the power control.

The hybrid phase shift keying (HPSK) modulation [Reference Springer and Wigel9] used by W-CDMA causes fast changes in the envelope h. The statistic properties of h are derived from simulation results of a HPSK modulator implemented in MATLAB^®. This method is preferred over an analytic model because of the high complexity of the modulation scheme. The simulation uses the 768 kb/s uplink reference measurement setup, which is given by the 3^rd generation partnership project (3GPP) [10], and uniform distributed random input data. The probability density function (pdf) $p_F\lpar h\comma \; \dot{h}\comma \; \ddot{h}\rpar $ represents the fast changes caused by the modulation and results from the analysis of 3.84 × 10⁵ chips with 16 samples per chip. Its isosurface p _F = 1 is depicted in Fig. 4. The shape in the middle of the diagram, which looks like a spinning, represents smooth changes in the envelope. The two arcs are caused by large and fast changes of h. The power control of a mobile terminal adapts the RF output power P_O to the radio signal propagation conditions. Figure 3 depicts the pdf p _S (P_O), which demonstrates that the PA rarely operates at its maximum output power P_Om. The following equation combines p _F and p _S:

(30)$$p_M\lpar h\comma \; \, \dot{h}\comma \; \, \ddot{h}\rpar = \mathop \vint \nolimits_{0}^{\bar {P}_{Om}} p_s\lpar \bar{P}_o\rpar p_F\left(\xi h\comma \; \xi \dot{h}\comma \; \xi \ddot{h}\right)\, d\bar{P}_o\eqno\lpar30\rpar$$

$${\rm with}\; \xi \lpar \bar P_{O} \rpar = \sqrt {\displaystyle{{\bar P_O } \over {\bar P_{Om} }}}.$$

Fig. 3.

The probability density function of the PA RF output power [Reference Sahu and Rinćon-Mora6] for W-CDMA.

Fig. 4.

Isosurface (p _F = 1) which reflects the fluctuation of the envelope h due to modulation. The variable f _C denotes the W-CMDA chip rate of 3.84 MHz.

Now, all the statistic properties of h, needed for the optimization of the design, are characterized.

C) Optimization of the design parameter

Altogether five parameters (Δt, L, C, τ, and V _DD) and the dimension of the power switches completely describe the modeled buck converter. To find their optimal values, first of all the switching frequency f _S of the DC–DC converter has to be specified. To achieve a low ripple on the PA supply voltage, this value should be much higher than the corner frequency of the output low-pass filter (formed by the inductor L and the capacitor C). On the other hand, the efficiency of the buck converter decreases with rising switching frequency, is due to the dynamic losses in the power switches, which are proportional to f _S. Additionally, the available semiconductor technology limits the switching frequency. In contrast to a PWM controlled buck converter, f _S of the proposed design is not constant, but a function of the circuit input signal. Hence, the maximum switching frequency f _SM, which can be approximated by the following rule of thumb (assuming that A ₋ ≈ A ₊ ≈ A and x _2k ≈ x _2k + 1):

(31)$$f_{{SM}}={\rm max}\, f_{2k} \mathop \approx \limits^{\left({12} \right)} \displaystyle{{c^T e^{ - A\Delta t} \left({b_ - - b_+} \right)} \over {4c^T \left({e^{ - A\Delta t} - 1} \right)\left({x_+- x_ - } \right)}} \approx \displaystyle{1 \over {4\Delta t}}\eqno\lpar31\rpar$$

will be taken into account. For the deployed IBM BiCMOS 7WL technology, a maximum switching frequency of 50 MHz provides an ideal trade-off between low output ripple and high efficiency. So according to (31) the delay of the control circuit Δt equals 5 ns.

In order to combine the results of the mathematical model and the statistic properties of the envelope the state x _2k of the buck converter has to be defined

(32)$$\eqalign{x_{2k}&=\left({\matrix{ {I_{2k} } & {V_{E} } \cr } } \right)^T \cr {\rm with}\, I_{2k}&=\displaystyle{{V_E } \over {R_L }} - \displaystyle{C \over {\beta _0 }}\left[{\left({\alpha _{0.5} \!-\! \alpha _0 } \right)V_{E}+\beta _{0.5} \dot V_{E}+\gamma _{0.5} \!-\! \gamma _0 } \right].}\eqno\lpar 32\rpar$$

The DC–DC converter is able to follow the envelope signal, as long as the series of t _k is monotonically increasing. This condition is fulfilled, if the denominators of (10) and (11) are both positive. The first equation describes the span of time during which the output voltage V is falling to the desired value. The linearity of the PA is not affected if the supply voltage decreases too slowly. Much more critical is such behavior during the rise of V, which is indicated by a negative denominator of (11). To avoid these operation states, the supply voltage has to fulfill the following relation:

(33)$$V_{{DD}}\gt \displaystyle{{LC} \over {\beta _1 }}\left[{c^T {e}^{ - A_+ \Delta t} \left({A_+x_{2k+1} - \displaystyle{{I_L } \over C}e_V^T } \right)- \dot V_S } \right]\eqno\lpar33\rpar$$

(34)$$\hskip -47pt={a_3}{\ddot V}_E +{a_2}{\dot V}_E+{a_1}V_E+a_0.\eqno\lpar34\rpar$$

To achieve preferably small values of V _DD, the damping δ₊ should be minimal. So the requirement

(35)$$C = \displaystyle{L \over {R_+R_L }}\eqno\lpar35\rpar$$

reduces the dimension of the parameter space by one. The PA-dependent voltage V _H, V ₀, and V _Emin establishes the connection between the input voltage of the buck converter V _E and the normalized envelope:

(36)$$V_{E}=\left\{{\matrix{ {V_{{Emin}} }\comma \; \hfill & {V_{H} h+V_0\lt V_{{Emin}}\comma \; } \hfill \cr {V_{H} h+V_0 } \hfill & {{\rm otherwise}}. \hfill \cr } } \right.\eqno\lpar36\rpar$$

The probability, that the supply voltage V _DD does not satisfy (33) during n of N switching cycles, is

(37)$$P_{V} \lpar V_{{DD}} \rpar =\mathop {\lim }\limits_{N \to \infty } \displaystyle{n \over N}=1 - \mathop \vint \nolimits_{ - \infty }^\infty p_{V} \lpar V_{{DD}}\rpar \, {d}V_{{DD}} .\eqno\lpar37\rpar$$

Thereby, the probability density function p _V is derived from the envelope statistic in the following way:

(38)$$p_V \left({V_{DD} } \right)= \vint_{ - \infty }^\infty {\vint_{ - \infty }^\infty {p_F \left({h^*\comma \; \dot h\comma \; \ddot h} \right)\,d\dot h \, d\ddot h\comma \; } } \eqno\lpar38\rpar$$

(39)$$h^* = \displaystyle{1 \over {a_1 }}\left[{\displaystyle{{V_{DD} - a_0 - a_1 V_0 } \over {V_H }} - a_2 \dot h - a_3 \ddot h} \right].\eqno\lpar39\rpar$$

The coefficients a ₀, a ₁, a ₂, and a ₃, which are required to evaluate h*, result from equating the corresponding coefficients of (33) and (34). The diagram in Fig. 5 shows P _V as a function of the output filter's corner frequency f ₀ for different supply voltagesFootnote ¹ It shows, that f ₀ and V _DD are interchangeable: the same dynamic behavior can be achieved with a low corner frequency and a high supply voltage and the other way around. To keep the output ripple of the buck converter low, the value of f ₀ should be at least five times lower than the maximum switching frequency f _SM. By setting τ = 20τ_Crit the stability of the circuit is ensured. With respect to these requirements, the values, which are marked in Fig. 5 with a cross, were chosen for V _DD and f ₀. The power switches are a chain of tapered CMOS inverters (tapering factor v = 9). So the transistors parameters can be derived from the parameters of the last inverter, which consists of p- and nMOSFETs. To minimize the parasitic capacitances and the channel resistance their length has been set to the technology minimum of 400 nm. Hence, the remaining parameters are the width of the p- (w _p) and the nMOSFET (w _n). The values of the model parameter R ₊, R ₋ and E _SW are calculated by transient simulations for varying values of w _p and w _n. The mathematical model allows to calculate the loses P _L of the DC–DC converter and the DC power used by the PA P _U in the following way:

(40)$$\overline P _{L/U} \left({w_p \comma \; w_n } \right)= \vint {P_{L/U} \left({h\comma \; \dot h\comma \; \ddot h} \right)} p_M \left({h\comma \; \dot h\comma \; \ddot h} \right)\,dh \, d\dot h \, d\ddot h\vert _{w_p \comma w_n }\comma \; \eqno\lpar40\rpar$$

Fig. 5.

The probability, that the DC–DC converter is not able to follow the envelope signal as a function of the supply voltage V _DD = {1.9 V,1.95 V,2 V,2.05 V} and the corner frequency f ₀ of the output filter.

where $P_{L/U}\lpar h\comma \; {\dot h}\comma \; {\ddot h}\rpar $ is equivalent to P _L/U(x _2k) from (27) and (28), respectively, with x _2k according to (32) and (36). Out of these two quantities the efficiency of the buck converter can be determined easily by

(41)$$\eta _{B}=\displaystyle{{\bar P_U } \over {\bar P_U+\bar P_L }}.\eqno\lpar41\rpar$$

Its value is depicted in Fig. 6 as a function of w _p and w _n. The cross marks the configuration, which was chosen for the design. It is a little bit displaced to the maximum, to avoid too large values of R ₊ and R ₋, which downgrade the P _V (V _DD). A summary of all design parameters is given in Table 1.

Fig. 6.

Contour plot of the buck converter efficiency η_B versus the dimension of the power switches.

Table 1.

Summary of the optimized parameters.

A) Envelope detector

The circuit of this block is well known as diode detector. The block capacitor C ₀ decouples the DC part of the RF input signal. Only the positive half-wave of the remaining signal passes the Schottky diode D1. An RC filter, which consists of R ₁, R ₂, C ₁, and C ₂ suppresses the carrier of the W-CDMA modulated RF signal and implements the derivation in (17). Its transfer function has a pole of order two at f ₁ = 15 MHZ which is about four times higher than the chip rate of the W-CDMA signal and a simple zero at

(42)$$f_2=\displaystyle{{\alpha _{0.5} } \over {2\pi \beta _{0.5} }}=\displaystyle{{\alpha _{0.5} } \over {2\pi R_2 C_2 }}=2.31\, {\rm MHz}.\eqno\lpar42\rpar$$

Thus, a good carrier rejection is achieved, and simultaneously the distortion of the envelope signal is acceptable. The comparator uses current signals. Hence, a current mirror transfers the current through R ₁ (output signal of the RC filter) to the envelope detector output current I ₋. To avoid an input power dependent offset of this signal, a dummy diode detector is employed. The minimal output voltage of the buck converter V ₀ is adjusted by the external resistor R ₃.

B) Comparator

The output current of the proportional differential feedback I ₊ is inverted by a current mirror and fed to the input of a CMOS inverter (T1 and T2). Thus, the input current of the inverter is the difference ΔI between the I ₊ and I ₋, the output currents of the proportional differential feedback and the envelope detector. This small part of the whole block already shows the desired behavior: if ΔI is negative the inverter output switches to the supply voltage or else to ground. To increase the speed of the comparator a chain of multiple stages with low gain is preferred over one stage with a high gain [Reference Chen, Shi and Lu11]. Hence, the gain of the inverter is reduced by degeneration. For this purpose, T3 is operated in linear region to form a feedback resistor. Two adjacent common-source stages compensate the gain losses due to the degeneration. With the help of this technique a very low delay time of 1.9 ns is achieved. The output of the last source stage drives a chain of seven CMOS inverters. Three of them belong to the comparator. They ensure that the input signal of the power switches, formed by the remaining four inverters, is rail to rail.

C) Power switches

As already mentioned the power switches are formed by a chain of four tapered CMOS Inverters. They have a separate voltage supply to avoid interferences with the other blocks of the circuit. About 65% of the chip area (without pads) is occupied by them. Figure 6 shows the configuration of the power switches, which are an optimum trade-off between efficiency and speed. In this configuration the pMOSFET of the biggest inverter in the tapered chain has a width of w ₊ = 7100 µm and the corresponding nMOSFET has a width of w ₋ = 5900 µm. The dimensions of the driver stages in the chain result from the tapering factor v = 9 and are listed in Table 2.

Table 2.

Dimension of the driver stages of the power switches.

In conjunction with the comparator transient simulations show a total delay Δt of 4 ns. To compensate process variations, this value is consciously a little bit smaller than the one calculated in Section II(C).

D) Proportional differential feedback

To make the design more flexible, the feedback circuit processes an input signal range between zero and 1 V. In doing so the ratio between the envelope of the RF input signal and the output voltage V is adjustable by an external voltage divider (R ₄ and R ₅). Although the PA parameter V _H can be fine tuned during the measurements. As the comparator requires a current signal, the input voltage is converted to the output current I ₊ by a source follower. The capacitor C ₃ in its load impedance induces the desired differentiating behavior

(43)$$\tau = R_6 C_3 = 90\, {\rm ns}.\eqno\lpar43\rpar$$

A level shifter, which consists of T4 and T5, guarantees that the transistor of the adjacent source follower does not leave the saturation region over the complete input voltage range.

A) Model parameters of the buck converter

In order to quantify the resistances R ₊ and R ₋ of the power switches, the input V _Sens of the chip is connected to an external voltage source. By increasing or rather decreasing its voltage, the state of the power switches can be toggle. A constant current source is applied to the output of the buck converter. For both states of the switches its current is swept from −200 to 200 mA. Through the measurement of the output voltage V two voltage–current characteristics arise. Each of them is approximated well by a linear function, whose slope is equal to the resistance in demand.

To find out the value of the time constant τ, the input V _Sens is connected to a sine wave generator. The amplitude and offset of this generator are chosen in a way, that the power switches can be fixed in both states (without any further switching cycles) by varying the bias current I _B. For different frequencies f of the sine wave I _B is adjusted, until the power switches stop changing their state and only the one, which connects the output of the chip to ground, is active. After a sweep over a frequency range from 100 to 10 MHz the amplitude of the generator is set to zero (its offset is maintained). The bias current is adjusted like before and its value is assigned to the variable I _B0. The approximation of the measurements by the function

(44)$$I_B \lpar \,f\rpar = I_{B0} - K \lpar 1 + \tau 2\pi f\rpar \comma \; \eqno\lpar44\rpar$$

results in the demanded time constant.

In an additional measurement, the buck converter is operated without a load (I _L = 0 and R _L → ∞). Its output voltage V is set by means of an RF signal generator, which feeds an unmodulated 1.95 GHz carrier with the power P_I in the input of the envelope detector. The output of the power switches is connected to an oscilloscope. It is used to measure the period of time Δt ₀ during which the switch to the supply voltage is active and Δt ₁ vice versa. Furthermore, the average current I_DD drained from the source V _DD is recorded. Because the input voltage V _E of the DC–DC converter remains constant during each measurement, its state x ₀ has to fulfill the following equation:

(45)$$x_0 = {\cal T}_{\Delta t_1}^+ {\cal T}_{\Delta t_0}^{-} x_0. \eqno\lpar45\rpar$$

So x ₀ and the corresponding state x ₁ after the time Δt ₀ can be calculated as follows:

(46)$$x_0 = \left(E - {\rm e}^{A_+ \Delta t_1} e^{A_ - \Delta t_0} \right)^{ - 1} {\cal T}_{\Delta t_1}^+ {\cal T}_{\Delta t_0}^{-} 0\comma \; \eqno\lpar46\rpar$$

(47)$$x_1 = {\cal T}_{\Delta t_0}^{-} x_0. \eqno\lpar47\rpar$$

Due to V _E = const. the equation

(48)$$c^T \left({\cal T}_{ - \Delta t}^{+} x_0 - {\cal T}_{ - \Delta t}^ - x_1 \right)= 0 \eqno\lpar48\rpar$$

is valid. It is used to obtain the value of Δt, because all other variables it contains are already known.

The dynamic losses of the power switches can also be derived from the measured data

(49)$$P_{SW} \lpar f_0\rpar = E_{SW} f_0 = V_{DD} \bar{I}_{DD} - \left({\cal L}_{\Delta t_0}^{-} x_0 + {\cal L}_{\Delta t_1}^{+} x_1 \right)f_0. \eqno\lpar49\rpar$$

With the help of this relation, E _SW can be calculated easily. To get more accurate results, the shown procedure is repeated for different output voltages V. Table 1 summarizes the measured parameters of the buck converter. The parameters specified during the design of the circuit and the measured ones match well.

B) Complete system

Now the designed circuit is used to modulate the supply voltage of a commercial standard W-CDMA PA (RMPA2265). Because this PA is a two-stage design, only its second and final stage is connected to the buck converter. Its first stage is supplied by a constant supply voltage and is neglected in the following considerations. The RMPA2265 is operated in the low-power mode, which has a linear output power of 16 dBm. Two properties have to be determined for the PA with a fixed supply voltage and the EF configuration: the efficiency and the linearity. The efficiency is defined as the ratio of the complete system power consumption and the output power of the PA. To compare both configurations the efficiency gain

(50)$$G = {\eta_{EF} \over \eta} \eqno\lpar50\rpar$$

is introduced. In this equation, η_EF enotes the efficiency of the EF configuration and η describes the efficiency of the PA with a fixed supply voltage. As a measure for the linearity of the PA the adjacent channel leakage power ratio (ACLR) of its output signal is used. It is measured by a R&S^® FSU 67 spectrum analyzer in the first and second, left and right adjacent channel. The W-CDMA modulated test signalFootnote ², which feeds the PA, is generated by a R&S^® SMBV100A vector signal generator. Figure 10 depicts the results of the measurements. It shows a significant efficiency gain at low output powers P_O. The values of G can also be calculated with the mathematical model of the buck converter

Fig. 10.

Comparison between the fixed supply voltage and the EF (with the proposed buck converter and an ideal supply voltage modulator) configuration of the RMPA 2265.

$$G = {\vint \left({V_E \lpar \xi h\rpar \over R_L} - I_L \right)V_E \lpar \xi h\rpar p_F \lpar h\comma \; \dot{h}\comma \; \ddot{h}\rpar \, dh \, d \dot{h} \, d \ddot{h} \over \vint \left(P_U \lpar \xi h\comma \; \xi \dot{h}\comma \; \xi \ddot{h}\rpar + P_L \lpar \xi h\comma \; \xi \dot{h}\comma \; \xi \ddot{h}\rpar \right)p_F \lpar h\comma \; \dot{h}\comma \; \ddot{h}\rpar \, dh \, d\dot{h} \, d \ddot{h}}\comma \;$$

(51)$${\rm with}\; \xi = \sqrt{{\bar{P}_O \over \bar{P}_{Om}}}\comma \; \quad{\bar{P}_{Om}} = 16\, \hbox{dBm}. \eqno\lpar51\rpar$$

The forecast of the model matches the measurements very well. This is quite impressive, considering that a simplified and linearized model was used for analysis. The ACLR leaves slightly the range admitted by the W-CDMA standard. This effect can have two different causes: either the DC–DC converter is not capable to follow the envelope of the RF input signal all the time. Or the gain and phase shift of the PA changes with its supply voltage. Such behavior, which was shown for the RMPA2265, makes it not very suitable for an EF PA at all. To emphasize this assumption the ACLR estimation method, presented in [Reference Sundstrom12], is applied on a RMPA2265 whose supply voltage is modulated ideally. The results are also depicted in Fig. 10. They show that even an ideal modulation of the supply voltage would cause a significant rise of the ACLR. Due to the dependency of the PA gain and phase on its supply voltage, the output ripple of the buck converter is mixed with the RF signal. This effect causes the high values of the ACLR (especially at low output powers) in the second adjacent channels. The following properties of the design were observed with an oscilloscope and are completely satisfying.

The average efficiency gain

(52)$$\bar{G} = \vint p_S \left(\bar{P}_O {P_{27dBm} \over P_{16dBm}} \right)G \lpar \bar{P}_O\rpar \, d\bar{P}_O = 2.03\eqno\lpar52\rpar$$

is obtained by weighting the measured values with their probability. Furthermore, the average efficiency gain with an ideal supply voltage modulator is defined as follows:

(53)$$\bar{G}_I = \vint {V_{DD} \over V_E \lpar \xi h\rpar } p_M \lpar h\comma \; \dot{h}\comma \; \ddot{h}\rpar \, dh \, d\dot{h} \, d\ddot{h} = 3.19. \eqno\lpar53\rpar$$

The ratio between these two quantities is approximately the efficiency of the buck converter

(54)$${\bar{G} \over \bar{G}_I} \approx \eta_B = 63.8\percnt . \eqno\lpar54\rpar$$

The value of η_B as also derived from the results of the measurements and is very similar to the one which was determined during the parameter optimization (shown in Fig. 6 with a cross).