Overview of 3D integration technology

Several thinned LSI chips with through-Si vias (TSVs) and metal microbumps can be vertically stacked in a 3D LSI. 3D integration technology is classified into three categories based on the TSV fabrication process, namely, via-first, via-middle, and via-last. The via-middle and back-via type via-last methods are widely used to fabricate 3D LSIs.^{Reference Koyanagi4} In the via-middle process, deep trenches are formed by reactive ion etching (RIE) after transistor formation. After forming the oxide liner, barrier metal layer, and Cu seed layer inside the trenches, these deep trenches are filled with Cu by electroplating. Then, multilevel metallization layers are formed on the TSVs after Cu chemical mechanical polishing (CMP). Next, CuSn or CuSnAg microbumps are formed, and the LSI wafer with Cu-TSVs is temporarily bonded onto a support wafer and thinned from the backside by mechanical grinding and CMP. After exposing the bottom of the Cu-TSV and forming CuSn or CuSnAg on it, the support wafer is de-bonded from the thinned LSI wafer. Finally, thinned chips with Cu-TSVs and metal microbumps are stacked onto a Si interposer or organic substrate. A Si interposer is used to integrate several chips that are interconnected by the redistributed metal lines formed on it. A typical example of a TSV fabricated by the via-middle process is shown in more detail in Reference 5.

In the back-via process, Cu-TSVs are fabricated after the Si substrate is thinned. First, the LSI wafer with metal microbumps is temporarily bonded onto a support wafer, the Si substrate is thinned, and then the deep trench is formed from the backside by RIE. The interlayer dielectric under the first level metallization exposed at the bottom of the deep trench is then etched off by RIE to expose the first level metallization layer (M1), and the oxide liner is deposited. This process step is followed by selective etching of the oxide liner at the bottom of the deep trench to expose, again, M1. Next, the deep trench is filled with Cu by electroplating after the formation of a barrier metal layer, such as a Ta layer and a Cu seed layer. Metal microbumps are also formed on the backside of the Cu–TSV. The support wafer is de-bonded from the thinned LSI wafer, and, finally, thinned chips with Cu–TSVs and metal microbumps are stacked on a Si interposer or organic substrate. A typical example of TSV fabricated by the back-via process is shown in Reference 6. A small production of 3D LSIs for dynamic random access memory as represented by the hybrid memory cube and high bandwidth memory has started.^{Reference Kang, Chung, Heo, Ahn, Lee, Cha, Ahn, Kwon, Kim, Lee, Joo, Kim, Kim, Lee, Kim, Ma, Jang, Kim, Choi, Oh, Lee, Jung, Yoo and Kim7–Reference Suh10}

Heterogeneous 3D integration and super-chips

A very attractive feature in 3D LSI is the capability of heterogeneous integration. Different kinds of chips can be integrated into one stacked chip. Such heterogeneous 3D integration provides the possibility to achieve new functional LSIs.^{Reference Fernández-Bolaños and Ionescu11,Reference Taklo, Ramm, Fleischer, Ionescu and Pufall12} Typical examples of heterogeneous 3D integration are the integration of a MEMS chip on a CMOS chip and the integration of an optoelectronic chip on a CMOS chip that can be used as an intelligent sensor and high-performance microprocessor, respectively. A super-chip is also an example of heterogeneous 3D integration for IoT applications. A super-chip can be achieved by stacking various types of chips with different sizes, devices, and materials, as shown in Figure 1. So far, prototype super-chips have been fabricated by stacking MEMS chips, spin memory chips, and photonic device chips on CMOS chips.

Figure 1.

Configuration of a super-chip. Note: RF IC, radio frequency integrated circuit; IC, integrated circuit; LSI, large-scale integration; DRAM, dynamic random-access memory; SRAM, static random-access memory; MEMS, microelectromechanical system.^{Reference Fukushima, Yamada, Kikuchi and Koyanagi2}

Figure 2 shows a super-chip where a CMOS chip is stacked on an LSI wafer, and a pressure sensor MEMS chip is integrated onto the CMOS chip.^{Reference Lee, Noriki, Kiyoyama, Fukushima, Tanaka and Koyanagi13} A self-assembly technique, described later, was used to fabricate this super-chip. Figure 3 shows a spin memory (spin transfer torque memory) chip stacked on a CMOS chip with static random access memory and reconfigurable logic circuits in a super-chip, where spin memory is used as a configuration memory for reconfigurable logic circuits.^{Reference Tanaka, Kino, Nakazawa, Kiyoyama, Ohno and Koyanagi14} Spin memory is a new non-volatile memory with high speed memory access capability. A magnetic tunneling junction (MTJ) is used in a memory cell of the spin memory. As is clear from the current (I) versus voltage (V) characteristics in Figure 3, MTJ showed excellent switching behavior with a high resistive state and a low resistive state even after 3D stacking.

Figure 2.

Photomicrograph of microelectromechanical system (MEMS) stacked on a complementary metal oxide semiconductor chip. Note: LSI, large-scale integration.^{Reference Lee, Noriki, Kiyoyama, Fukushima, Tanaka and Koyanagi13}

Figure 3.

A spin (STT) memory chip stacked on a complementary metal oxide semiconductor chip with static random access memory (SRAM) and reconfigurable logic. (upper left) Cross-sectional structure, (lower right) scanning electron microscope cross-section of a through-Si via (TSV) formed in spin memory chip, and (upper right) current (I) versus voltage (V) characteristics of magnetic tunneling junction (MTJ) after 3D stacking. Note: MOSFET, metal oxide semiconductor field-effect transistor.^{Reference Tanaka, Kino, Nakazawa, Kiyoyama, Ohno and Koyanagi14}

Figure 4 shows a 3D optoelectronic LSI where an optoelectronic integrated circuit chip with Si photonic devices is stacked on CMOS chips.^{Reference Lee, Noriki, Kiyoyama, Kanno, Kobayashi, Jeong, Bea, Fukushima, Tanaka and Koyanagi15,Reference Noriki, Lee, Bea, Fukushima, Tanaka and Koyanagi16} The respective chip layers are vertically connected by both optical interconnections (TSPV, through-Si photonic vias) and electrical interconnections (TSV, through-Si vias). A Si optical waveguide with an oxide cladding layer is used as a TSPV. In order to fabricate TSV and TSPV, a cylindrical deep trench and a ring-type deep trench are simultaneously formed by RIE. Then The Cu-TSV is formed by the process described earlier, whereas the Si-TSPV is formed by filling the ring-type deep trench with silicon oxide or organic material. Thus, the Si-TSPV and Cu-TSV are simultaneously fabricated in a heterogeneous 3D integration process, as shown in Figure 4. We confirmed that an optical signal is effectively guided by the TSPV. An optical grating coupler with a mirror was used to change the propagation direction of the optical signal. A high coupling efficiency of more than 80% in this optical grating coupler was obtained, which is sufficient for high speed optical data transfer. Continuous propagation of the optical signal from the vertical TSPV to the horizontal Si waveguide through the optical grating coupler has been confirmed.

Figure 4.

Three-dimensional (3D) optoelectronic large-scale integration (LSI). (upper left) Structure of 3D optoelectronic LSI, (lower left) cross-sectional view of through-Si photonic via (TSPV) and through-Si via (TSV), (upper right) structure (upper figure) and surface view (lower figure) of optical grating coupler with a mirror, and (lower right) 2D map of optical energy propagated from TSPV to optical grating coupler where the red color indicates higher energy (simulation).^{Reference Lee, Noriki, Kiyoyama, Kanno, Kobayashi, Jeong, Bea, Fukushima, Tanaka and Koyanagi15,Reference Noriki, Lee, Bea, Fukushima, Tanaka and Koyanagi16}

Figure 5 shows a 3D stacked artificial retina chip for a retinal prosthesis.^{Reference Deguchi, Watanabe, Nakamura, Nakagawa, Fukushima, Shim, Kurino and Koyanagi17} A 3D stacked artificial retina chip with three stacked layers was fabricated and implanted into the eyes of a rabbit. We succeeded in observing the electrically evoked potential in the rabbit’s brain after electrical stimulation of ganglion cells by the implanted 3D stacked artificial retina chip. Ganglion cells are retina output cells that send visual signals to the visual cortex in the brain. The observation of an electrically induced potential means that visual signals are transferred from the implanted retina chip to the visual cortex, thus visual sense is regenerated in the brain.

Figure 5.

Configuration of three-dimensional stacked complementary metal oxide semiconductor image sensor chip for retinal prosthesis (artificial retina).^{Reference Deguchi, Watanabe, Nakamura, Nakagawa, Fukushima, Shim, Kurino and Koyanagi17}

Self-assembly and electrostatic bonding

A new heterogeneous 3D integration technology to fabricate a super-chip using SAE temporary bonding has been developed, which can provide high production throughput. This technology has been named reconfigured wafer-to-wafer (RW2W) 3D integration technology.^{Reference Fukushima, Kikuchi, Yamada, Konno, Liang, Sasaki, Inamura, Tanaka and Koyanagi18,Reference Fukushima, Iwata, Ohara, Noriki, Inamura, Lee, Bea, Tanaka and Koyanagi19} First, more than several hundred known good dies (KGDs) are sorted from several device wafers and then simultaneously bonded in a batch, with a high alignment accuracy of 1 μm, onto a carrier wafer using SAE temporary bonding. High alignment accuracy in SAE bonding is indispensable for forming a high density of electrical connections between the upper and lower chips. This carrier wafer, which consists of many KGDs, is called a reconfigured wafer, and it exhibits very high production yield because of the KGDs. Next, another reconfigured wafer is fabricated by simultaneously bonding many KGDs onto another carrier wafer. We can produce many reconfigured wafers by repeating this procedure. These reconfigured wafers are stacked onto a target interposer wafer at the wafer level. Several hundred super-chips with different configurations can be simultaneously fabricated on a 12-inch wafer with high production throughput and low cost by using the RW2W integration technology.

The surface tension of a liquid is utilized in self-assembly to simultaneously align many dies in parallel. Hydrophilic areas and hydrophobic areas are formed on the surface of a wafer or chip to obtain high alignment accuracy. Hydrophilicity and hydrophobicity are evaluated by measuring the contact angle of a water droplet on the surface. The contact angle of the hydrophilic area is smaller than 30°, whereas that of the hydrophobic area is larger than 110°. Liquid droplets are simultaneously formed on the hydrophilic areas that are the bonding areas, and then many chips are simultaneously supplied onto the hydrophilic areas in the self-assembly process. We have succeeded in simultaneously aligning five hundred chips with an average alignment accuracy of 0.5 μm within 0.1 s, which gives rise to a high bonding speed of 5000 chips/s. In contrast, conventional chip bonding machines provide low bonding speeds of 0.1 to 1 chip/s, depending on the alignment accuracy of 1 to 10 μm.

In the RW2W integration technology, it is necessary to temporarily bond many chips onto a carrier wafer after simultaneously aligning them by self-assembly. After de-bonding, these chips are simultaneously transferred to a support wafer. Therefore, temporarily bonding and de-bonding are very important steps in RW2W integration technology. An electrostatic temporary bonding and debonding method has been developed for the RW2W integration technology.^{Reference Fukushima, Hashiguchi, Bea, Ohara, Murugesan, Lee, Tanaka and Koyanagi20} Many chips are simultaneously bonded onto the electrostatic carrier (e-carrier) wafer by electrostatic force after simultaneous alignment by self-assembly, as shown in Figure 6. The electrostatic force for temporary bonding is generated by applying a high voltage of 200 V to the electrodes embedded in the e-carrier. A high voltage with opposite polarity is applied to the electrodes for debonding chips. The SAE carrier is used for both self-assembly and electrostatic temporary bonding in the RW2W integration. Many chips are simultaneously face-up bonded onto the SAE carrier using SAE bonding, and then a support wafer is bonded on the chips using an adhesive. Chips with the support wafer are then debonded from the SAE carrier by applying a voltage with opposite polarity. Thus, many chips are simultaneously transferred from the SAE carrier to the support wafer. Transferred chips are thinned from the backside to form TSVs and metal microbumps, and then the target interposer wafer is bonded on the thinned chips with TSVs and metal microbumps. The support wafer is then removed from thinned chips/target interposer wafer for further stacking of chips. Super-chips can be fabricated by repeating this sequence.

Figure 6.

Hybrid self-assembly using self-assembly and electrostatic (SAE) temporary bonding. Note: KGD, known good die; SAE, self-assembly and electrostatic; CA, contact angle.^{Reference Fukushima, Kikuchi, Yamada, Konno, Liang, Sasaki, Inamura, Tanaka and Koyanagi18–Reference Fukushima, Hashiguchi, Bea, Ohara, Murugesan, Lee, Tanaka and Koyanagi20}

3D image sensor system module for advanced driving assistant system

A 3D image sensor system module for an advanced driving assistant system is shown in Figure 7, where a pair of 3D stacked CIS chips and several 3D stacked multicore processors are integrated on a Si interposer. High performance image processing using stereo vision for image recognition and obstacle detection is indispensable to guarantee safety while driving using the driving assistant system in an automobile. A pair of 3D stacked CIS chips are used to provide stereo vision images with a high data rate of 10,000 frames/s. CIS chips have already been used to capture rear views in automobiles. However, a conventional 2D CIS chip cannot provide stereo vision images at such a high data rate. Three-dimensional stacked multicore processors are used to process the very large amount of data provided from a pair of 3D stacked CIS chips with high speed and low power. Parallel processing is indispensable to achieve high speed and low power operation in multicore processors. The 3D stacked structure is necessary for the high performance parallel processing. Fabrication was carried out using the RW2W integration technology with SAE bonding.^{Reference Lee, Ohara, Kiyoyama, Konno, Sato, Watanabe, Yabata, Kamada, Bea, Hashimoto, Murugesan, Fukushima, Tanaka and Koyanagi21,Reference Koyanagi22}

Figure 7.

Configuration of a 3D image sensor system module for an advanced driving assistant system. Note: ADC, analog-to-digital converter.^{Reference Koyanagi4,Reference Lee, Ohara, Kiyoyama, Konno, Sato, Watanabe, Yabata, Kamada, Bea, Hashimoto, Murugesan, Fukushima, Tanaka and Koyanagi21,Reference Koyanagi22}

Figure 8 shows a 3D x-ray computed tomography (CT) scan image of a fabricated 3D stacked CIS chip.^{Reference Koyanagi4} It is obvious in the image that the fabricated 3D stacked CIS chip has a layered structure with four layers where TSVs with a diameter of 5 μm and a length of 50 μm are clearly observed. Excellent block parallel operation performance with a high frame rate of 10,000 frames/s was confirmed in the fabricated 3D stacked CIS chip. A highly dependable 3D multicore processor for the 3D image sensor system module has been proposed. This 3D multicore processor has a new self-test and self-repair function to achieve high dependability. New built-in self-test circuits and self-repair circuits are embedded in each processor core. Processor chips are self-tested and self-repaired on-time using these circuits. It was estimated that a high dependability of 80 Fits can be achieved using such a new on-time self-test and self-repair function. The processor chip was designed and fabricated by 90 nm CMOS technology. A four-layer stacked 3D memory and multicore processor device was fabricated.

Figure 8.

Three-dimensional x-ray computed tomography scan image (right image) and scanning electron microscope cross-sectional view of a through-Si via (TSV) (left image) obtained from a 3D stacked complementary metal oxide semiconductor image sensor chip fabricated by reconfigured wafer-to-wafer integration technology.^{Reference Koyanagi4,Reference Lee, Ohara, Kiyoyama, Konno, Sato, Watanabe, Yabata, Kamada, Bea, Hashimoto, Murugesan, Fukushima, Tanaka and Koyanagi21,Reference Koyanagi22}

Figure 9 shows a photo-micrograph and an x-ray CT scan image of a TSV array for a four-layer stacked multicore processor.^{Reference Koyanagi22} TSVs with a diameter of 8 μm and a length of 50 μm are clearly observed. A scanning electron microscopy cross-sectional view for two layers is also shown in Figure 9. Excellent performance for the fabricated 3D multicore processor was confirmed. Thus, a 3D stacked CIS chip and 3D stacked multicore processor was successfully fabricated by RW2W integration technology. A two-layer stacked CIS chip with backside illumination has been fabricated and commercialized as well.

Figure 9.

(a) Photomicrographs of four-layer stacked three-dimensional (3D) memory and multicore processor. (b) Scanning electron microscope (SEM) cross-sectional view (upper figure) and x-ray computed tomography (CT) scan image of a through-Si via (TSV) array for a 3D multicore processor (lower figure). Note: TEG, test element group; RDL, redistribution layer; I/O, input/output.^{Reference Koyanagi4,Reference Lee, Hashimoto, Onishi, Konno, Sato, Nagai, Bea, Murugesan, Fukushima, Tanaka and Koyanagi6,Reference Lee, Ohara, Kiyoyama, Konno, Sato, Watanabe, Yabata, Kamada, Bea, Hashimoto, Murugesan, Fukushima, Tanaka and Koyanagi21,Reference Koyanagi22}

Summary

Various applications are expected for 3D LSIs in the IoT era since 3D LSI has many advantages, such as high performance, low power, multifunctionality, and small form factor. Heterogeneous 3D integration is expected to further expand the application area of 3D LSIs. Several types of LSI chips with different sizes, devices, and materials can be heterogeneously integrated to fabricate a super-chip. A new RW2W 3D integration technology using SAE temporary bonding has been developed to fabricate super-chips with high production throughput and yield.