I. INTRODUCTION
Since the emerging of GaN technology as a promising alternative for high-power high-frequency high electron-mobility transistor (HEMT) devices, due to its higher power density and thermal conductivity with respect to GaAs [Reference Sheppard1–Reference Wu3], investigations about a large-signal model (LSM) for GaN HEMTs have been a frequent research field. Empirical or measurement-based models, whose parameters are related to physical effects taking place in the transistor, are usually the favored approach over models based solely on physical device properties and dimensions or black-box models, because they allow both efficient simulations and complex descriptions of nonlinear effects. Typically, LSMs contain a set of intrinsic parameters that are deduced from the small-signal model (SSM) variations with respect to the operation conditions (bias and temperature). This intrinsic part of the transistor is embedded in an extrinsic element network (EEN), which is also part of the SSM. Therefore the correct identification of the SSM is an essential task to obtain an accurate LSM.
II. FOREWORD TO THE PROPOSED LSM
The first step to identify the bias-dependent SSM is the extraction of the EEN. It has been found that standard methods used for the respective GaAs FETs modeling (with the “Cold-FET” technique) are not directly applicable to large-size GaN HEMTs, due to the high parasitic capacitances effects inherent to this technology [Reference Burm, Schaff, Eastman, Amano and Akasaki4, Reference Zarate-de Landa, Zuniga-Juarez, Loo-Yau, Reynoso-Hernandez, Maya-Sanchez and del Valle-Padilla5]. These complex parasitic effects lead to the proposed EEN displayed in Fig. 1 [Reference Jarndal and Kompa6], especially focusing on the development of a later scalable SSM.
Proposed equivalent circuits for GaN HEMTs: (a) extrinsic element network, (b) intrinsic small-signal model elements, and (c) intrinsic large-signal model elements.
Some algorithms published for SSM extraction of GaN HEMTs with a simpler EEN tend to lack generality. They may correspond to particular transistors with improved low-resistive ohmic contacts, as in [Reference Crupi7], or may use forward gate bias to suppress capacitive effects [Reference Chigaeva8], simplifying the EEN and the SSM extraction algorithm. The latter case requires a positive V GS unsafe for the transistor. Other works contain technological suppositions that are not generally applicable, as in [Reference Chen, Kumar, Schwindt and Adesida9], while some algorithms without forward biasing consider the pinch-off depletion region with geometrical conditions that only correspond to specific devices [Reference Brady, Oxley and Brazil10, Reference Nuttinck, Gebara, Laskar, Shealy and Harris11]. Extraction of the extrinsic effects is eased if passive “dummy” structures are available, as in [Reference Crupi7, Reference Chen, Kumar, Schwindt and Adesida9], but generally they are not.
The proposed SSM equivalent circuit is presented in Figs 1(a) and 1(b). It exhibits a high correlation between the EEN and the physical parasitic effects in the device. As usual, the EEN is considered to be independent of frequency and biasing. The intrinsic elements in small- and large-signal are frequency independent but dependent on the bias voltages V GS and V DS. In the proposed modeling methodology, the EEN is extracted from pinch-off S-parameter measurements as shown in Section III.
The bias dependency of the small-signal intrinsic elements is obtained from S-parameter measurements on a set of bias points covering the I DS–V DS plane as shown in Section IV.
The non-quasi-static large-signal current and charge sources of the gate are found by integration over small-signal intrinsic capacitances and conductances as shown in Section IV.
The bias-dependent parameters of the I DS model for trapping mechanisms and self-heating are calculated from pulsed-DC measurements as shown in Section V, including also the extraction of the electro-thermal parameters.
Section VI will show the model verifications on different large-signal operation modes.
Section VII contains the final conclusions of this work.
III. PROPOSED ALGORITHM FOR THE EXTRACTION OF THE EXTRINSIC ELEMENTS OF THE SSM
In this work, the idea of scanning sets of capacitance distribution, aiming to minimize an error function, will be used to find reliable element values of the physics-correlated EEN based on S-parameter measurements at pinch-off. The values extracted in this first stage already give an excellent agreement of measurements and simulations in the low-frequency range dominated by capacitive effects. To extend the validity of the EEN into higher frequencies the distribution of the capacitance values initially found is improved in a second phase using optimization. This two-stage strategy avoids the local minima problem. The idea of scanning sets of capacitance distribution employed in the first stage is clarified in Section B, but before that, the physical interpretation of the proposed EEN is detailed in Section A. The generation of the values of a capacitance distribution for each scan step is shown in Section C. For a given capacitance distribution, Sections D and E detail the extraction of extrinsic inductances and resistances. Section F describes the last step of the first stage, which is the evaluation of the SSM for a given scan step. It also presents results of applying the extraction algorithm on measurements of an actual GaN HEMT. Section G deals with a final second stage, where optimization around the vicinity of the global minimum is used to refine the extracted EEN.
A) Physical meaning of the extrinsic capacitors in the EEN of the proposed SSM
In the adopted circuit, the layer of a-subscripted capacitors represents capacitances associated with the gate and drain contact pads, while the layer of i-subscripted capacitors denote capacitances related to the gate and drain fingers.
– C pda and C pga represent, as usual, the capacitances between the gate and drain pads and ground;
– C gda denotes the capacitance between the drain fingers and the gate pad;
– C gdi is the capacitance between the gate and drain fingers;
– C pgi stands for the capacitance between the gate fingers and the source pads (also the capacitance between the gate fingers and the air-bridge if it exists);
– C pdi denotes the capacitance between the drain fingers and the source pads (also the capacitance between the drain fingers and the air-bridge if it exists).
B) Idea of scanning the capacitance distribution
The parasitic capacitances dominate the low-frequency S-parameters of the pinched-off transistor, with zero drain bias. Via S- to Y-parameter conversion, the total capacitance among the gate–drain, gate–source, and drain–source branches can be obtained. The total capacitance value of each branch must be distributed into three values, two extrinsic and one intrinsic. Each capacitance distribution has specific extrinsic resistances, inductances, and intrinsic elements associated.
Given a comprehensive set of capacitance distributions, the associated SSMs can be evaluated with a properly formulated error function. The lowest error will correspond with the optimal SSM and its capacitance distribution. Because the three values that can be calculated for the total branch capacitances must be distributed to nine unknowns, further equations must be derived to eliminate degrees of freedom of the equation system and find a unique solution, thereby obtaining the best capacitance distribution. Additionally, degrees of freedom may be eliminated by scanning a range of values that a given extrinsic capacitance could take. Clearly, the scanning range is limited by the total capacitance of the corresponding branch and zero. For each scan step, all other extrinsic and intrinsic elements will be calculated to evaluate the error function for the whole resulting SSM.
C) Distribution of total branch capacitances for a scan step
Figure 2 shows the transistor equivalent circuit at sufficiently low-frequency (f ≤ f cap) at pinch-off (V GS < V pinch-off, V DS = 0 V). The measured S-parameters in this frequency range are converted to Y-parameters, [Y p], and the total branch capacitances are obtained from the imaginary parts of [Y p] with the next expressions:
where Y 12p = Y 21p.
Equivalent circuit for the pinched-off transistor at low frequencies.
Given that C gda and C pga are scanned from 0 to C gd0 and from 0 to max{C gs0, C ds0}, respectively, the following assumptions complete the equations system of (1)–(3) to find all the values of the corresponding capacitance distribution:
Equation (4) assumes that the depletion region under the gate with at pinch-off is uniform. Equation (5) implies that the capacitances of the drain and gate pads are similar. In equation (6) the capacitance between the gate and drain fingers is considered to be nearly twice the capacitance between the gate and drain pads. Typically, the capacitance between the drain finger and the source pads is larger than the capacitance of the drain pad to ground, as denoted in equation (7). The specific ratio given in (7) was found empirically to reduce the error function values. A more analytical way to find this ratio using a top-view of the device and the expression of a parallel-plate capacitor (C = є rє 0·A/d) has been developed, but is thought to be beyond the scope of this work and will be published later.
For each scan step the complete capacitance distribution can be calculated with equations (1)–(7), the next step is to determine the associated extrinsic inductances and resistances.
D) Extraction of extrinsic inductances for a specific capacitance distribution
According to Caddemi et al. [Reference Caddemi, Crupi and Donato12], the intrinsic transistor at pinch-off can be modeled by a “T”-type capacitive circuit. Thus after removing the effects of C pga, C pda, and C gda from the pinch-off measurement the corresponding equivalent circuit of the transistor is shown in Fig. 3(a). This representation can be converted in the one given in Fig. 3(b) by well-known Π–T and T–Π network transformations. The imaginary parts of the associated Z-matrix can be expressed by
Equivalent circuit of the pinched-off transistor after removing the a-subscripted capacitances: (a) with “T”-type intrinsic version, (b) equivalent representation after Π–T and T–Π network transformations.
The inductance values can be obtained by linear data fitting.
E) Extraction of extrinsic resistances for a specific capacitance distribution
To calculate the extrinsic resistance values associated with the capacitance distribution, all the extrinsic capacitive and inductive effects are removed from the pinch-off measurement, and then the result is converted to impedance parameters. The real parts of the obtained matrix are related to R g, R d, and R s by
For scanned capacitance distributions different from the optimal one, residual terms may appear in these real parts with nonlinear frequency dependence. Such effects are reduced by multiplying equations (11)–(13) by ω 2, receiving
F) Evaluating the capacitance distributions and finding the reliable SSM based on S-parameter measurements at pinch-off
After all the extrinsic elements values of the scanned capacitance distribution have been found, the related admittance matrix of the intrinsic transistor can be calculated and all intrinsic elements can be derived by well-known equations, as in [Reference Zarate-de Landa, Zuniga-Juarez, Loo-Yau, Reynoso-Hernandez, Maya-Sanchez and del Valle-Padilla5].
The S-parameters of the complete SSM of the given capacitance distribution are then reconstructed and compared with the measurements to evaluate the error function:
where W ij = max|S ij|, i,j = 1,2; i ≠ j; W ij = 1 + max|S ii|, i = 1, 2; and N is the number of frequency points.
It has been pointed out in the past that the reliability of the resistances extracted from pinch-off measurements was unsure, due to strong capacitive effect dominance and errors related to noisy S-parameter measurements of the transistor at pinch-off. The main unwanted result of this situation was the appearance of frequency-dependent residuals on the real parts for resistances calculation (equations (11) and (12)). Usually, as explained in the introduction, a cold-forward S-parameter measurement (with high positive V GS) is used to better estimate the values of the extrinsic resistances. However, with correct on-wafer calibration and correct estimation of the capacitance distribution, the undesired frequency-dependent residuals of Re[Z] vanish ([Z] is the impedance matrix used for resistance value extraction from S-parameters at pinch-off).
Moreover, the intrinsic transistor equivalent circuit shown in Fig. 3(a) implies that Im[Z int]−1 = ω C. Thus, only the correct estimation of the reactive parasitic effects properly minimizes any higher-order frequency-dependency of Im[Z int]−1.
Therefore, after removing the extrinsic elements for the optimal capacitance distribution, the standard deviation of the Re[Z] and of Im[ω Z int]−1 is reduced to its minimum. Consequently, these standard deviations are calculated for each scan step, normalized (to have no units), and added to the error function. This increases the certainty of the resistance extraction, while avoiding the need of an extra S-parameter measurements with high positive gate bias.
The capacitance distribution that gives the minimum value of the error function, of all that were scanned, corresponds to the optimal SSM element values than can be obtained based on pinch-off S-parameters.
Results of applying the algorithm on an actual GaN HEMT are displayed next. The device under study has eight gate fingers, with gate width of 400 µm and gate length of 0.5 µm for each finger. The device was fabricated by the Fraunhofer Institute for Applied Physics (IAF, Freiburg). Table 1 lists the best values of the SSM extracted from pinch-off measurements.
Best SSM value set extracted from the pinch-off measurements.
Figure 4(a) depicts the measured low-frequency Y-parameters of the transistor at pinch-off converted from S-parameters and the respective values of C gs0, C ds0, and C gd0 for (1)–(3). Figure 4(b) shows the measured data of equations (8)–(10) for the calculation of the inductance values. Figure 4(c) presents the measured data for computation of the resistance values. Figure 4(d) displays the frequency dependence of the extracted intrinsic elements in pinch-off.
Results of the application of the algorithm with measured data of a 3.2-mm gate-width GaN HEMT in pinch-off operation: (a) capacitance extraction, (b) inductance extraction, (c) resistance extraction, and (d) intrinsic elements extraction.
G) Optimization refinement of the extrinsic elements extracted from pinch-off S-parameter measurements.
The proximity of the extracted extrinsic elements to the true optimal value is assured by the consistent formulation of the algorithm. They are further refined by optimization procedure. In this way the numerical resolution of the extracted extrinsic values is increased and also fractional deviations from the used assumptions (equations (4)–(7)) are taken into account.
The extrinsic parameters are the optimization space, and their values extracted from measurements are the starting point. The overall SSM can be calculated in each iteration, as explained in the previous sections. A constrained optimization algorithm is used (simplex variation of [Reference Kompa and Novotny13]).
Table 2 contains the parameter values of the optimized SSM, and Fig. 5 shows the comparison of the S-parameters of the optimized SSM and the measurements at pinch-off.
S-parameter comparison between the final extracted SSM predictions (lines) and the measurements at pinch-off with zero drain voltage (markers).
SSM value set after optimization refinement.
IV. CALCULATION OF THE INTRINSIC SMALL-SIGNAL MODEL AND THE NON-QUASI STATIC LARGE-SIGNAL SOURCES
The effects of the EEN found in previous sections can be removed from the S-parameter measurements on each desired bias point to find the Y-parameters of the intrinsic transistor. Figure 6 shows the expected frequency independence of the extracted intrinsic parameters.
Frequency dependence of intrinsic elements for the 3.2-mm GaN HEMT (V GS = −1.0 V, V DS = 5.0 V).
All the intrinsic elements of the SSM, shown in Fig. 1(b), may be calculated directly from the Y-parameters of the intrinsic transistor in a standard manner. The bias-dependencies of the main intrinsic elements that were computed for the transistor under study are shown in Fig. 7, where the variations in terms of the bias voltages may be observed as expected, for example with opening the channel, conduction increases, the transit time of the electron through the channel decreases, as well as the electrostatic separation between drain and source (increasing capacitance); thus, G ds, C ds, and τ change inversely with respect to V GS.
Extracted small-signal intrinsic elements for the 3.2-mm GaN HEMT.
The non-quasi-static large-signal current and charge sources represent the conduction and displacement currents on the gate node, respectively, while their combination with R i and R gd stands for the non-instantaneous response of the charge in the channel under the gate with respect to fast changes of the input voltages. The proposed topology for these sources of the gate reflects the symmetrical character of the transistor for low V DS and at pinch-off. Numerical path-integration of the C gs, C gd, and C ds with respect to the bias voltages gives the bias dependency of the Q gs and Q gd values. In a similar way I gs and I gd are obtained from G gsf and G gdf. The integration formulation used after [Reference Kompa14] is
where (V gs0, V ds0) is an arbitrary integration starting point.
The resulting sets of values are shown in Fig. 8. In previous works, it was necessary to further apply a numerical mapping to express these parameters with respect to the intrinsic voltages V ds and V gs (bias voltages in the intrinsic transistor terminals) instead of expressing them in terms of extrinsic voltages V DS and V GS (the measured bias voltages), in which they are directly computed. This surface re-gridding usually bears numerical inconsistencies, especially for devices with large extrinsic resistances, and introduced uncertainty in the values of the final intrinsic parameters for low-V DS or high-I DS regions. In this work, the capabilities of the ADS© SDDs (symbolically-defined devices [15]) to user-define the control voltages of the model components are exploited, to directly control the table-based parameters, in the model implementation, with the extrinsic voltages present on the transistor during simulation. As a result the extrinsic-to-intrinsic voltage mappings and their problems are avoided.
Computed parameters of the I DS model for the 3.2-mm GaN HEMT.
V. EXTRACTION OF IDS MODEL PARAMETERS FROM PULSED-DC MEASUREMENTS
GaN HEMTs tend to present low-frequency dispersion of the I DS current that is a compression of the RF I–V curves with respect to DC. This phenomenon has been related to charge trapping mechanisms and device self-heating. Following the approach of Filicori et al. [Reference Filicori, Vannini, Santarelli, Sanchez, Tazon and Newport16], trapping induced dispersion is assumed to be controlled by DC components of the instantaneous voltages v ds and v gs applied to transistor, whereas self-heating induced dispersion is considered to be dependent of the temperature changes on the channel and of the transistor thermal response, and therefore the proposed I DS model can be expressed by
The bias dependencies of I DS,iso (isothermal current) and the trapping-related parameters f G and f D can be calculated from a set of pulsed-DC measurements with non-power-dissipative quiescent bias points: (V GS0 = 0 V, V DS0 = 0 V), (V GS0 < V P, V DS0 = 0 V) and (V GS0 < V P, V DS0 > >0 V), as in [Reference Filicori, Vannini, Santarelli, Sanchez, Tazon and Newport16]. For the GaN HEMT under study, these bias points correspond to (V GS0 = 0 V, V DS0 = 0 V), (V GS0 = −6 V, V DS0 = 0 V), and (V GS0 = −6 V, V DS0 = 60 V). The computed parameters related to charge-trapping induced current dispersion are shown in Fig. 8.
According to Filicori et al. [Reference Filicori, Vannini, Santarelli, Sanchez, Tazon and Newport16], f thR th can be calculated using measurements with quiescent bias points where the dissipated power is non-zero and a reference measurement without self-heating effects, i.e. (V GS0 = 0 V, V DS0 = 0 V). The measurements used with P diss ≠ 0 were (V GS0 = −3 V, V DS0 = 40 V), (V GS0 = −2.5 V, V DS0 = 30 V), and (V GS0 = −3.25 V, V DS0 = 50 V), with dissipated power of approximately 7.4, 11.9, and 4.4 W, respectively. The computed parameter related to self-heating induced current dispersion is displayed in Fig. 8.
Pulsed-DC measurements of the transistor under study presented instabilities in regions with high P Diss and high G m. During unstable DC-operation the measurement system may stop responding which involves a risk of damaging the device or the system, by unsafely terminating the measurements, besides the risk of damage due to current peaks. Moreover, the instabilities limit the achievable dataset for the I DS model development and constrain the LSM accuracy and region of validity. A built-in feature of the available pulsed-DC system (DiVA D265EP by Accent®) allows the calibration of the measurement error produced by including a stabilization resistor. For FETs it is recommended to use a resistor in shunt to ground with the drain. The stabilization effect decreases as the shunt resistor increases with respect to the transistor output impedance. The resistance value used was 110 Ω and was obtained empirically (the transistor output impedance in DC was found to be around 60 Ω). Although applying the calibration method incorporated in the measuring system, there is a residual error in the computation of the actual I DS that can be attributed to the stabilization of the transistor. This effect has been taken into account in the later simulations of the LSM as a slight shift of the operation bias point (V DS, I DS), of up to a 10% of the nominal values.
The term ΔT, a temperature difference, is a function of the dissipated power P diss (I DSV DS) and the thermal parameters C th and R th as shown in the thermal sub-circuit of Fig. 1(c).
An accurate estimation of the thermal sub-circuit parameters C th and R th is obtained using a direct numerical simulation technique. The device thermal profile of the equivalent physical topology of the AlGaN/GaN HEMT device is obtained through the implementation of the heat equation, taking into account the different types of heat transfer mechanisms, boundary conditions, and temperature dependent thermal conductivities of the composite materials. The dissipated power density is partitioned on the different fingers. It is included in the thermal procedure via the heat generation term in the heat transfer equation. The final result of the processed solution is a discrete matrix formulation including the thermal profile of the complete meshed structure, from which the thermal parameters are determined, for more details see [Reference Dahmani, Mengistu and Kompa17]. The thermal resistance R th is first obtained from the steady-state static DC simulation defined as [Reference Filippov and Balandin18],
where ΔT is the temperature difference as shown in the thermal profile of the HEMT structure as shown for a 3.2 mm device in Fig. 9, and P diss is the total dissipated power in the device. For a power dissipation of 7 W/mm the obtained R th is 14°C/W.
Thermal profile of a 3.2 mm (8 × 400 µm) HEMT structure, due to symmetry only four fingers are presented. The temperature gradient is higher at the channel under the gate.
The thermal capacitance C th is obtained from a transient DC power dissipation simulation, from which the thermal time constant can be deduced for individual fingers and total HEMT structure. This thermal time constant, obtained by a first-order curve fitting of the transient simulation as presented in Fig. 10, is used to evaluate the equivalent capacitance in the thermal RC model representation of the look-up table based electrical model. For the 3.2 mm device under study, the obtained thermal time constant is 85 µs (RthCth).
Transient thermal simulation and first order curve fitting for the central finger of the 8 × 400 µm HEMT device. Inset shows fast transient occurs for t < 5 µs.
Higher order RC equivalent thermal model can be implemented using this procedure [Reference Dahmani, Mengistu and Kompa19], as shown in Fig. 11 for the 3.2-mm transistor, to capture the fast temperature increase as depicted in the inset of Fig. 10.
Transient simulated data and exponential curve fitting for the 3.2 mm device (a) for individual fingers (b) and second-order curve fitting for the central finger.
VI. LSM VERIFICATION
The model is implemented in ADS® (Advanced Design System) software. The extrinsic elements are represented by lumped elements, as well as the parameters of the thermal sub-circuit. The bias dependent parameters Q gs, Q gd, I gs, I gd, R i, R gd, G ds, τ, I DS,iso, f G, f D, and f th are written as tables into files and implemented as DAC blocks (Data Access Components). As previously mentioned, SDD components are utilized to define the controlling variables, besides they are used to construct the intrinsic part of the large-signal equivalent circuit. Large-signal simulations were realized and compared with measurements of the 3.2-mm GaN HEMT. Pulsed-DC verification is shown in Fig. 12, with very good agreement between predictions and measurements at different quiescent bias voltages, it is worth mentioning that these quiescent bias points were not used for modeling.
Pulsed-DC comparison of measurements (markers) and simulations (lines) for the 3.2-mm GaN HEMT (measurement set not used in modeling). V GS from −3.9 to −0.3 V every 0.6 V.
Single-tone verification is shown in Fig. 13. The model error is less than 5–10% for fundamental output power and the first two harmonics. P out is correctly predicted up to nearly 36 dBm (4 W). The model prediction of third-order intermodulation products (IMD3) agrees acceptably with the measurements, as displayed in Fig. 14, it can be noted in this figure (plot for the second bias point) that the model is able to reproduce the sweet-spot phenomenon typically arising on this type of transistors for bias points towards pinch-off. The shift of the sweet-spot that can be observed between measurements and simulations is caused by the residual error received from the stabilization technique in the measurements of the dataset for the I DS model (Pulsed-DC), which introduces a slight uncertainty to identify the bias point in the simulation that corresponds with the verification measurements, particularly for bias points with low I DS.
Large-signal verification with single-tone stimulus (measurements – markers, simulations – lines) for the 3.2-mm GaN HEMT.
Large-signal verifications with two-tone stimulus in two bias points (measurements – markers, simulations – lines) for the 3.2-mm GaN HEMT.
VII. CONCLUSIONS
A large-signal modeling strategy for large gate periphery devices has been presented, based on proper identification of the underlying small-signal and I DS models from measurements. A distinctively comprehensive EEN has been proposed accounting for the complex parasitic effects that can be expected in transistors with large gate peripheries. The extraction algorithms have been clarified, and their consistency demonstrated, to allow their general application. Comparisons of large-signal measurements and harmonic-balance model predictions have been given for a GaN HEMT with 3.2-mm gate width in pulsed-DC, single-tone and two-tone operation regimes, showing accurate results and supporting the model suitability for high-ower amplifier design.
ACKNOWLEDGEMENTS
The authors thank M. Schlechtweg and R. Quay of the Fraunhofer Institute for Applied Physics (IAF, Freiburg) for supplying the GaN HEMTs, as well as S. R. Embar and B. Wittwer for their support in measurements. This work was supported by the German Ministry of Education and Research (BMBF), contract No. O1BU0610.
J. Alberto Zamudio-Flores was born in Mexico City, Mexico, in 1979. He received the electronics and telecommunications Engineer degree from the National Polytechnic Institute (IPN), in Mexico City, Mexico, in 2001. In 2005 he received the M.Sc. degree electronics and telecommunications with specialty in high frequency electronics from the Centre of Scientific Research and Higher Education of Ensenada (CICESE), Ensenada, Mexico. In 2005 he joined Autonomous University of Hidalgo State (UAEH) as Lecturer in the Department of Electronics, in Pachuca, Mexico. He is currently working to obtain his Ph.D. degree in electronics at the Microwaves Electronics Department, University of Kassel, Germany. His research work deals with the large-signal modeling of GaN HEMTs with large gate periphery for power amplifiers applied in modern mobile telecommunications. His research interests also include high efficiency power amplification techniques and noise modeling of field-effect transistors.
Günter Kompa received the Dipl.-Ing. and Dr.-Ing. degrees from the Technical University of Aachen, Aachen, Germany, in 1970 and 1975, respectively. In 1976, he was with Endress & Hauser, Maulburg, Germany, where he focused on microwave and laser radar research and development. Since 1984, he has been a Professor heading the Department of Microwave Technology, University of Kassel, Germany. From 1990 to 2002, he was a referee for the Federal Ministry of Education and Research (BMBF). From 1997 to 2001, he was a referee of the German Academic Exchange Service (DAAD). In 1997, he established the international masters course “Electrical Communication Engineering” at the University of Kassel, which belongs to the first established international postgraduate degree courses in Germany. His current research interests mainly cover circuit and system design of ultra-wideband microwave and laser radars, multi-tone characterization and modeling of high-power devices and amplifiers, and power amplifier linearization. He has authored or coauthored over 150 technical papers. He has filed numerous patents. Dr. Kompa was the recipient of the 1978 Heinrich-Hertz Award presented by the Institute of Radio and Electronic Engineers, London, U.K.
Samir Dahmani was born in 1971. He received the Engineer degree in electronics and electrical engineering, and the M.Sc. degree in electronic systems engineering from the National Institute for Electricity and Electronics (INELEC), Boumerdes, Algeria in 1994 and 1997, respectively. From January 1998 to November 2001, he was a Research Assistant with the Development Center for Advanced Technologies (CDTA), Algiers, Algeria. In December 2001, he joined as a Lecturer the Department of Electronics, University of Blida, Algeria. He is currently working towards his Ph.D. degree. His work is focused on RF electro-thermal modeling and characterization of GaN-based large-size high-power transistors at the Microwaves Electronics Department, University of Kassel, Germany.
