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Comparison of TRL, 8-, 10-, and 16-term on-wafer calibration methods for accurate SiGe HBT characterization up to 330 GHz

Published online by Cambridge University Press:  16 October 2026

Tarek Bouzar*
Affiliation:
University of Bordeaux, Talence, France
Jojo Varghese
Affiliation:
University of Bordeaux, Talence, France
Jean-Daniel Arnould
Affiliation:
University Grenoble Alpes, Grenoble INP, TIMA, Grenoble, France
Thomas Zimmer
Affiliation:
University of Bordeaux, Talence, France
Sebastien Fregonese
Affiliation:
University of Bordeaux, Talence, France
*
Corresponding author: Tarek Bouzar; Email: tarek.bouzar@u-bordeaux.fr
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Abstract

This paper discusses the challenges involved in characterizing high-frequency SiGe heterojunction bipolar transistors. Process engineers continually strive to enhance device performance by shrinking dimensions and minimizing parasitic capacitances; however, these capacitances – on the order of only a few femtofarads – are particularly susceptible to measurement errors. At millimeter-wave and sub-THz frequencies, the finite size and electromagnetic-field distribution of RF probes may lead to residual substrate coupling and probe-to-probe crosstalk, especially when the device under test and pad dimensions are strongly scaled. To investigate these issues, we apply on-wafer 16-term calibration techniques using accurately designed calibration standards. Starting from the full 16-term error-correction model and progressively simplifying it in a step-by-step manner, we compare the performance of 16-, 10-, and 8-term calibrations and, finally, traditional TRL calibration up to $330\,\text{GHz}$. We verify the consistency of these approaches, analyze their influence on the extraction of passive elements, and evaluate how each calibration scheme affects key transistor performance metrics, such as the maximum oscillation frequency ($f_{\max}$).

Information

Type
Research Paper
Creative Commons
Creative Common License - CCCreative Common License - BYCreative Common License - NCCreative Common License - ND
This is an Open Access article, distributed under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives licence (http://creativecommons.org/licenses/by-nc-nd/4.0), which permits non-commercial re-use, distribution, and reproduction in any medium, provided that no alterations are made and the original article is properly cited. The written permission of Cambridge University Press or the rights holder(s) must be obtained prior to any commercial use and/or adaptation of the article.
Copyright
© The Author(s), 2026. Published by Cambridge University Press in association with The European Microwave Association.
Figure 0

Figure 1. Flowgraph of full 16-term error model for four-port adapter.Figure 1 long description.

Figure 1

Table 1. Measurement system error types for the 16-term error modelTable 1 long description.

Figure 2

Figure 2. Flowgraph of 10-term error model for four-port adapter.Figure 2 long description.

Figure 3

Figure 3. Description of the layout of the structures: (a) thru and (b) short-load.Figure 3 long description.

Figure 4

Figure 4. Asymmetric equivalent circuits used for the de-embedding structures: (a) $\pi$π-model of the transistor-open structure and (b) $T$T-model of the transistor-short structure.

Figure 5

Figure 5. (a) $C_{11}$C11 and (b) $C_{12}$C12 capacitance of the transistor-open structure versus frequency; comparison of the different calibration methods.Figure 5 long description.

Figure 6

Figure 6. (a) $L_{0}$L0 and (b) $L_{1}$L1 inductance of the transistor-short versus frequency; comparison of the different calibration methods.Figure 6 long description.

Figure 7

Figure 7. (a) $R_{0}$R0 and (b) $R_{1}$R1 resistance of the transistor-short versus frequency; comparison of the different calibration methods.Figure 7 long description.

Figure 8

Figure 8. The extracted junction capacitances (a) $C_{BE}$CBE and (b) $C_{BC}$CBC versus frequency for the different calibration at $V_{BE}=0$VBE=0 V and $V_{CB}=0$VCB=0 V.

Figure 9

Figure 9. Real parts of the $Y$Y-parameters versus frequency of the transistor at $V_{BE}=0.9$VBE=0.9 V and $V_{CB}=0$VCB=0 V.Figure 9 long description.

Figure 10

Figure 10. Imaginary parts of the $Y$Y-parameters versus frequency of the transistor at $V_{BE}=0.9$VBE=0.9 V and $V_{CB}=0$VCB=0 V.Figure 10 long description.

Figure 11

Figure 11. Gain-bandwidth products used for the extraction of (a) $f_{T}$fT, represented by $f\,|H_{21}|$f|H21|, and (b) $f_{\max}$fmax, represented by $f\sqrt{U}$fU, versus frequency for the transistor at $V_{BE}=0.9$VBE=0.9 V and $V_{CB}=0$VCB=0 V.Figure 11 long description.