II. PROPOSED DESIGN

AC–DC conversion performed with diode(s) causes at least one diode forward threshold voltage, which can be expressed as

(1)$$\left\vert {V_{TH}} \right \vert + \sqrt {\displaystyle{{2I_D} \over {\mu C_{ox} \left( {\displaystyle{W \over L}} \right)}}} \;,$$

where V _TH is the metal-oxide-semiconductor (MOS) threshold voltage, μCox is the intrinsic transconductance, and W and L are the transistor width and length, respectively [Reference Ghovanloo and Najafi1], when a rectifier is implemented in complementary metal-oxide-semiconductor (CMOS) process. The diode forward threshold voltage considerably decreases the supply voltage VOUT to the implanted circuitry for a given transmitted power P _TX and coupling factor. This means that for a required VOUT and given distance between the reader and transponder, P _TX stemming from the current i _TX driving the primary power amplifier must be considerably increased as VOUT is ideally a monotonic function of i _TX [Reference Sauer, Stanacevic, Cauwenberghs and Thakor2]. The relationship between the device geometry ratios, specified system requirements for the current dissipated at the primary side i ₁, output voltage of the rectifier VOUT, and other parameters can be expressed as [Reference Rendon-Nava, Díaz-Méndez, Nino-de-Rivera, Calleja-Arriaga, Gil-Carrasco and Díaz-Alonso6]

(2)$$\eqalign{VOUT &= \displaystyle{{\displaystyle{R \over {1 + j\omega R{C_L}}}} \over {{R_L}}} \cr &\quad\cdot \displaystyle{{\omega k\sqrt {{L_1}{L_2}} } \over {\sqrt {{{\left( {\displaystyle{{\omega {L_2}} \over {{R_L}}} + \omega {R_1}{C_1}} \right)}^2} + } {{\left( {1 - {\omega ^2}{L_2}{C_1} + \displaystyle{{{R_1}} \over {{R_L}}}} \right)}^2}}}\cr &\quad\cdot {i_1},}$$

where L ₁, L ₂, R ₁, C ₁, and R _L are the primary inductance, secondary inductance, secondary parasitic resistance, secondary resonant capacitance, and secondary load, respectively. A rectifier implemented in modern CMOS process can be expected to have considerably reduced substrate leakage current compared with its counterpart implemented in bipolar junction transistors (BJTs) [Reference Ghovanloo and Najafi1, Reference Sauer, Stanacevic, Cauwenberghs and Thakor2].

In response to the efficiency degradation caused by the diode(s), several state-of-the-art works have been demonstrated in the literature. In [Reference Ghovanloo and Najafi1], the authors employed cross-coupled power N-channel metal-oxide-semiconductor (NMOS) transistors in place of the diode-connected counterparts in the conventional full-wave rectifier to reduce the voltage drop for charging the capacitive load connected with VOUT. The authors of [Reference Sauer, Stanacevic, Cauwenberghs and Thakor2] presented another similar design where latch-up can be thoroughly prevented by taking advantage of all p-transistor implementation, without the employment of additional auxiliary transistors used to ceaselessly tie the bodies of the PMOS transistors to the highest voltage levels compared with that in [Reference Ghovanloo and Najafi1]. A comparatively different solution, using two active diodes achieving almost zero forward-voltage drop to replace the diode-connected power PMOS transistors in those proposed in [Reference Ghovanloo and Najafi1] and [Reference Sauer, Stanacevic, Cauwenberghs and Thakor2], has recently been presented [Reference Chen, Chen and Liu7].

Despite one diode existing in the conventional full-wave rectifier is eliminated for any of the three rectifiers, they still suffer from one diode threshold voltage drop in their conduction loops when functional. For implanted medical transponders based on RFID technology to provide the researchers with internal information (telemetry for sending data outside body) – neural recording for example, the recorded neural signal after filtering and amplifying is digitally quantified prior to being transmitted for the most part, in order to achieve robust communication. The binary data representing the neural signal can be load-modulated on the secondary side and demodulated on the external primary side, known as the LSK back telemetry.

In general, when R, modeling the average resistance equivalent to the implanted active circuitry, is large, a parallel MOS switch to short the coil inductor on the secondary side ahead of the rectifier for a short period of time can be used for LSK [Reference Atluri and Ghovanloo5]. On the other hand, a series MOS switch can be used after the rectifier to open the loads when R is small, causing additional dropout voltage and consequently degrading the system energy efficiency when the switch is on [Reference Wang, Liu, Sivaprakasam and Kendir4].

As a matter of fact, either of the two conditions demands to minimize the resistance to the MOS switch in order for sufficiently small dropout voltage and sufficiently large impedance change of LSK, resulting in the penalty of huge area overhead. The design proposed in this paper incorporated an efficient back telemetry mechanism with the rectifier to not only thoroughly address the diode concern but also deal with the problems in the commonly used LSK technique, which will be detailed in the following paragraph.

Shown in Fig. 2(a) is the circuit schematic of the rectifier. It has two symmetrical parts the same as those shown in [Reference Chen, Chen and Liu7], with the exception of the connections of the power transistors, N1 and N2, and four 2:1 multiplexers. These multiplexers make it a rectifier with three operating modes Rectification (SC, OC = 0, 0), Open Coil (SC, OC = 0, 1), and Short Coil (SC, OC = 1, 0) [Reference Atluri and Ghovanloo5]. By symmetry, steady-state operation of the rectifier can be explained using only the left half part.

Fig. 2.

Proposed low-loss rectifier with built-in back telemetry mechanism. (a) Rectifier main body. (b) Schematic diagram of multiplexer.

When operated in Rectification, each multiplexer chooses its input “0” as the gate driving potential of the corresponding power MOS. During the first half part of each AC voltage source period (i.e. VCOILa rises from its wave trough to peak), N1 first turns on and creates a conduction path from the referred ground GND to VCOILb. According to the explanation of [Reference Chen, Chen and Liu7], the drain voltage of M4, namely the gate voltage of M1, will be VOUT − |Vt _M4|. MP1 then turns on when VCOILa > VOUT − |Vt _M4| + |Vt _M1|. It means that the drop-out voltage can be minimized if |Vt _M4| is close to |Vt _M1|.

On the other hand, during the second half part of each AC voltage source period, MP1 first becomes off as long as VOUT > VCOILa − |Vt _M3| + |Vt _M2|. When VCOILa − VCOILb < V t _N1, N1 then turns off and cuts the conduction loop short. M7 and M8 function as the auxiliary transistors seen before. In order for optimal AC–DC conversion efficiency, MR1–MR6 should be designed in small-width and long-length transistors.

Operation of the right half part is identical to that of the left half part except that VCOILa and VCOILb are interchanged in analysis. It is obvious that, for the proposed design, there exists no diode voltage drop in the course of charging C _L; thereupon the loss in AC–DC conversion is minimized compared with that presented in [Reference Chen, Chen and Liu7]. C _L and R, brushed and connected with gray lines, are the loads not on-chip. The modified circuit configuration of N1 and N2 is the key to the efficiency enhancement. The threshold voltage drop cancellation feature of the rectifier is competitive with those demonstrated in the literature. An innovative cancellation circuit has been proposed to compensate the voltage drop by applying an external bias [Reference Umeda, Yoshida, Sekine, Fujita, Suzuki and Otaka8]. The applied bias is between the gate and source terminal of the diodes. However, the circuit is not on-chip design. Further improvement on the cancellation circuit in [Reference Umeda, Yoshida, Sekine, Fujita, Suzuki and Otaka8] was investigated and achieved in [Reference Nakamoto9]. Despite its fully on-chip implementation, ferroelectric capacitor is needed and special process masks are unavoidable, resulting in potentially higher manufacturing cost. Our work can be designed completely in standard CMOS technology without special process masks.

When operated in Open Coil, the gates of MP1 and MP2 are driven by their body potentials, detaching the loads from receiver LC tank. This makes the coil on the secondary side faces high impedance, and ideally reduces the reflected impedance onto the external reader to its maximum value estimated by [Reference Atluri and Ghovanloo5]

(3)$$\displaystyle{{\omega ^2 k^2 L_1 L_2 \; \; \;} \over {R_2}}\!,$$

where k, L ₁, L₂, and R ₂ are the coupling factor, primary coil inductance, secondary coil inductance, and parasitic resistance of the secondary coil, respectively. As for the Short Coil mode, MP1 and MP2 behave as if they are in the Rectification mode except that N1 and N2 are kept on continuously (their gates follow the VOUT terminal), resulting in the reflected impedance onto the external reader ideally reaches its minimum value estimated by

(4)$$\displaystyle{{\omega ^2 k^2 L_1 L_2 \; \; \;} \over {\sqrt {R_2 ^2 + \left( {\omega L_2} \right)^2}}}\!.$$

In additional to the several details regarding rectifier operation, the used 2:1 multiplexers shown in Fig. 2(b), which converts the low-swing SW signal to the high-swing counterparts to fully pass the selected source signal to OUT, as well as the feedback keeper loop formed by MDP1–MDP10, which starts shunting current from one coil terminal to the other while the span voltage across the coil is higher than about 3.4 V [Reference Li and Liu10], should also be highlighted. The HSPICE simulation results of the 2:1 multiplexers demonstrating the functionality are shown in Fig. 3. It can be easily understood that the proposed rectifier, with the integrated multiplexers achieving built-in back telemetry inside, not only eliminates the additional switch size requirements for the conventional counterpart in either of minimizing the open-coil-used switch turn-on span voltage and maximizing the short-coil impedance change, but also theoretically reaches the maximally changeable impedance values in LSK.

Fig. 3.

Post-layout simulation results of 2:1 multiplexers.

III. EXPERIMENTAL SETUP AND RESULTS

We have implemented the proposed rectifier whose micrograph is shown in Fig. 4 in a 0.18 μm 1P6M standard CMOS process. The design occupies 0.049 mm². To measure the system, we have built a platform, shown in Fig. 5, using international rectifier corporation (IRF) power devices with resonant network at primary side. We have made hand-wound spiral coils with 16 turns at both sides for testing purpose. The pancake-shaped coils were made from copper wires and the transceiver was tuned to be operated at 2 MHz in carrier frequency for all the passive components involved. The primary and secondary sides were moved apart. The two coils were center-aligned. To give better insight into how good the performance of the system can be achieved, both coupling efficiency of the coils at various distances and their dropout percentage at various thicknesses of Ringer's solution in the middle between the two coils to emulate truly human biology nature have been carried out. The results shown in Fig. 6 can be used to provide a decent idea of the performance on the built platform.

Fig. 4.

Chip photomicrograph.

Fig. 5.

Measurement setup.

Fig. 6.

Coupling efficiency (in air) versus percentage drop (with the Ringer's solution in between). The symbols of “*” and “Δ” indicate “Percentage drop versus thickness” and “RMS coil voltage versus coil distance”, respectively.

In addition to the experimental results obtained from the transceiver coils and their connected resonant networks at the primary and secondary sides, the performance of the proposed CMOS rectifier with back telemetry should be characterized specifically to be given as proof of concept. The experimental conversion efficiency of the proposed rectifier versus R under a carrier frequency of 2 MHz, C _L = 0.1 μF, and |VCOILa − VCOILb|_peak = 3.3 V is shown in Fig. 7. For a fixed R of 1 kΩ, plots of the conversion efficiency data on several carrier frequencies are revealed in Fig. 8. The chosen carrier frequencies have been clinically demonstrated that they are acceptable and applicable to the medical implants [Reference Wang, Liu, Sivaprakasam and Kendir4, Reference Rendon-Nava, Díaz-Méndez, Nino-de-Rivera, Calleja-Arriaga, Gil-Carrasco and Díaz-Alonso6].

Fig. 7.

Conversion efficiency versus resistive load. VCE means voltage conversion efficiency.

Fig. 8.

Conversion efficiency with respect to carrier frequency.

With regards to the results, power conversion efficiency (PCE) of the proposed rectifier degrades significantly for smaller R, which can be attributed to acutely increased requirement for the power input to rectifier. PCE also degrades with increased R as the gradually decreased power transferred to the loads dominates. In addition, implemented has the conversion efficiency degrading with increased carrier frequency, mostly as a result of the monotonicity between the drop-out voltage of VOUT and carrier frequency. Figure 9 shows the oscilloscope trace of the fabricated rectifier IC demonstrating the short-coil LSK functionality. Similar waveforms have also been observed in the prototypical chip for open-coil functionality. In summary, proposed is competitive with those demonstrated in the literature, which can be established in Table 1.

Fig. 9.

Oscilloscope trace of the rectifier operating at short-coil mode.

Table 1.

Comparison table of measured rectifier results.

VCE, voltage conversion efficiency; PCE, power conversion efficiency

– Not available in terms of rectifier.

* Standard CMOS version of the design proposed in [Reference Ghovanloo and Najafi1].

According to Fig. 9(a) in [Reference Ghovanloo and Najafi1].

† With multiplexers achieving built-in back telemetry mechanism.

Despite the rectifier-only conversion efficiency of 90% recorded, more detail needs to be given to explain the end-to-end “DC-load efficiency”. Definition of the DC-load efficiency can be found in [Reference Pinuela, Yates, Lucyszyn and Mitcheson11]. The DC-load efficiency includes the driver efficiency at the transmitter, the coil coupling efficiency, the rectifier efficiency, and the regulator efficiency. The regulator, the circuit beneath the rectifier, can have many types of circuit structure and is not the focus of this paper. Its efficiency may vary significantly, depending on design and application. From our experimental setup, the class-E driver efficiency is about 67%, due to semiconductor losses. The average coil coupling efficiency at a distance of 0–6 cm is about 3% for our hand-made coils. Assuming that the regulator efficiency can be as high as 90% for a DC-DC converter, these can be used to obtain a DC-load efficiency of about 1.6%.