I. INTRODUCTION
GaAs-based heterojunction bipolar transistors (HBTs) are widely used for power amplifiers in today's wireless communication systems. This technology offers high power density, high efficiency, and high linearity. But the increasing demand for high performance puts a stringent requirement for the device ruggedness [Reference Wang1–Reference Lee, Chau, Ma and Wang6]. A clear understanding of GaAs HBTs' safe operating areas (SOAs) and an accurate way to characterize them are extremely important.
Recently, the SOAs of industrially fabricated InGaP/GaAs HBTs have been intensively studied [Reference Tao, Lee, Denis and Henderson4, Reference Lee, Tao and Lin7]. A typically measured SOA boundary under DC operation for an intrinsic device (with no added ballasting resistors) is shown in Fig. 1, in which with stepping constant base voltage: V b mode (a) or constant base current: I b mode (b), and sweeping the collector voltage, the collector current density is monitored until the device fails as denoted with red dots. For V b mode two distinct regions are clearly seen in the SOA boundary. One region is at high current and low voltage and the other one at low current and high voltage. The I–V characteristics before failures in these two regions are very different. At low voltage and high current, the current goes up quickly with V ce , reaches a maximum, and then comes down before it fails. At low current and high voltage, however, the current usually bends up before it fails. The analytical modeling in [Reference Lee, Tao and Lin7] has successfully demonstrated the same phenomenon as observed experimentally. It shows that at low voltage and high current, the failure is controlled by the impact ionization because of the Kirk effect induced breakdown (KIB) (Kirk effect occurs when the mobile carrier density exceeds the space charge density in the collector causing the base push-out and electric field reversal [Reference Kirk8]), and at low current and high voltage, the failure is governed by the self-heating effect. The physical picture of the device operation around SOA boundary, however, could not be clearly illustrated with the simplified analytical models. For I b mode the phenomenon of current “hogging” in two-finger devices has been experimentally found [Reference Liu9], but to the authors' knowledge, it has never been numerically demonstrated with Technology Computer-Aided Design (TCAD). Most interestingly Fig. 1 shows that SOA boundaries for V b and I b modes are different, which also needs to be demonstrated with TCAD.
SOA measurements at room temperature for devices of emitter area 2 × 2 × 6 µm2 with constant V b (a) and I b (b) inputs. The red dots indicate the failure points the envelop of which defines the boundary of the SOA [7]. The current bent-over or snapback following each failure point is not shown here.
TCAD tool has been well recognized for revealing the operational mechanisms of the compound semiconductor devices [Reference Palankovski, Wagner and Selberherr10, Reference Tao and Bolognesi11] owing to its fundamental physical models. In this work, we perform two-dimensional (2D) numerical simulations using TCAD tool, for the first time, to investigate the mechanisms of HBT's SOA formation, and theoretically demonstrate our experimental findings.
II. 2D SIMULATION SETUP
The TCAD tool Sentaurus is used for the simulation of a InGaP/GaAs HBT as shown in Fig. 2. The epi-layers are typical in the industry as described in [Reference Lee, Tao and Lin7]. The substrate thickness is 300 µm and lateral width on one side is 200 µm, which emulates the real device die under test.
Schematic InGaP/GaAs HBT layout of a single emitter finger for 2D simulations. Two-finger device is symmetrical with respect to the vertical dash line on the right side.
Hydrodynamic model that accounts for the energy transport between the carriers and lattice is used [12], so that the device is heated up by the energy transferred from electrons to the lattice. The carrier generation rate due to the impact ionization (ii) is expressed by
$$G_{ii}=\alpha _n \cdot n \cdot v_n+\alpha _p \cdot p \cdot v_p\comma \; $$
where n and p denote the electron and hole, respectively, α n and α p are the impact ionization coefficients, and v n and v p are the velocities. An empirical model is used for α n and α p :
$$\alpha _{n\comma p}=a_{n\comma p} F\lpar {1+c_{n\comma p} {\rm \Delta }T} \rpar \exp \left[{ - \left({\displaystyle{{b_{n\comma p} \lpar {1+d_{n\comma p} {\rm \Delta }T} \rpar } \over F}} \right)^{\delta_{n\comma p} } } \right]\comma \; $$
where a n , p , b n , p , c n , p , d n , p , and δ n , p are coefficients, ΔT is the lattice temperature difference from 300 K, and F is the effective electric field that is dependent on the carrier temperature [12]. Generally the ii ratio for GaAs decreases with the temperature. The coefficient values are based on the reported data [Reference Ghin, David, Hopkinson, Pate, Rees and Robson13] but adjusted according to our breakdown measurement. To verify the aforementioned ii model we performed BV cbo (emitter opened) simulation and the collector current exhibits very steep increase at collector voltage of ~24 V, which is aligned with our BV cbo breakdown voltage (24 − 25 V) in manufacturing [Reference Lee, Tao and Lin7].
Energy band gap shrinks with increasing temperature and is calculated using
$$E_g=E_{g0} - {{\alpha \cdot T^2 } / {\lpar {\beta+T} \rpar }}\comma \; $$
where E g 0 is the band gap at temperature of zero, and α, β are coefficients. The band gap of ternary materials such as In x Ga 1−x P is calculated by
$$E_{g\lpar InGaP\rpar }=xE_{g\lpar InP\rpar }+\lpar {1 - x} \rpar E_{g\lpar GaP\rpar }+C_g \cdot x\lpar {1 - x} \rpar \comma \; $$
where E g(InP) and E g(GaP) are the band gaps of InP and GaP, respectively, and C g is the bowing parameter [Reference Palankovski and Quay14]. The low-field mobility is doping concentration (N) and temperature (T) dependent and expressed as [Reference Sotoodeh, Khalid and Rezazadeh15]
$$\mu=\mu _{min}+\displaystyle{{\mu _{max} \lpar {{T / {300k}}} \rpar ^\alpha - \mu _{min} } \over {1+\lpar {\lpar {{N / {N_0 }}} \rpar \lpar {{{300k} / T}} \rpar^\beta } \rpar ^\lambda }}\comma \; $$
where μ min , μ max , α, β, and λ are the coefficients. The lattice thermal conductivity is expressed by
$$k_L=k_{300} \cdot \left({\displaystyle{{T_L } \over {300k}}} \right)^\alpha\comma \; $$
where k 300 is the thermal conductivity at 300 K and α is a coefficient. k L for ternary materials is calculated by the interpolation of the two basic materials in the same fashion as abovementioned energy band gap. The lattice-specific heat is assumed to be constant since the data show that it has no significant variation above 300 K [Reference Palankovski and Quay14]. All the parameters and coefficients are defined based on either publicized data or our own measurements.
For the thermal boundary conditions, we define a constant temperature of 300 K on the backside of the substrate, and a thermal dissipation surface simply on top of the emitter metal due to the thick metal stack right on top of the emitter in real devices.
III. RESULTS AND DISCUSSION
A) Constant V b mode
The simulated collector current density (J c ) as a function of collector voltage (V ce ) with stepping constant V be from 1.3 to 1.5 V is shown in Fig. 3. The solid red dots are the failure points where the J c exhibits bent-over or snapback which is identical to the measurement [Reference Tao, Lee, Denis and Henderson4, Reference Lee, Tao and Lin7]. The boundary of SOA that is formed with these failure points demonstrates two distinct regions as experimentally shown in Fig. 1: one is of low currents and high voltages, and the other is of high currents and low voltages.
Simulated collector current density versus collector voltage for a 24 µm2 emitter area device with constant V b inputs. The red solid dots indicate the failure points that define the SOA boundary.
Let us first look at the device operations around failure points 1 and 4, which represent two different SOA regions. Figure 4 shows the calculated effective electric field in the collector along the center line of the device (see Fig. 2) at failure points 1 and 4. The normalized distance of zero and one indicate the base/collector and collector/sub-collector junctions, respectively. For comparison, the simulated field at the condition of BV cbo as described previously is also displayed It should be noted that the field we are referring is so called “effective electric field” associated with electron's temperature or energy, which is different from the conventional electric field, because hydrodynamic transport model is used in the tool [12]. Therefore the peak field (~3.3E5 V/cm) can be approximately considered as an avalanche threshold in our device. It is obvious that impact ionization is not responsible for the failure at point 1, since the effective field (<1.5E5 V/cm) is way below the aforementioned avalanche threshold. At point 4, however, the peak field is located at collector/sub-collector junction due to Kirk effect (to be discussed next) and the field strength is almost the same as the avalanche threshold. This shows that the impact ionization is responsible for the failure at point 4.
Simulated effective electric field from base/collector junction to collector/sub-collector junction at three bias conditions: (1) (blue triangles) BV cbo of around 24 V, (2) (red squares) the failure point of V be = 1.325 and V ce = 11.1 denoted as “1” in Fig. 3, and (3) (green diamond) the failure point of V be = 1.5 V and V ce = 2.7 V denoted as “4” in Fig. 3.
To further reveal the physical mechanism for the high-current and low-voltage region which seems to be very unique, we study two more bias conditions indicated by points 2 and 3 in Fig. 3. The simulated 2D profiles of effective electric field for the points 2, 3, and 4 are shown in Fig. 5. With increasing collector current from points 2 to 3, the Kirk effect occurs and the peak field moves from the base/collector junction toward sub-collector at point 3. Then the collector current drops due to severe base push-out and at point 4, the field becomes so high at collector/sub-collector that avalanche breakdown occurs.
Simulated effective field (V/cm) distributions for the point 2 (a), point 3 (b), and point 4 that is also failure point (c) in Fig. 3. The upper and lower boundaries of the collector are base/collector and collector/sub-collector junctions, respectively.
Here we need to answer an intuitive question. Is the failure because the temperature is so high that the device is burned? Figure 6 shows the output power density (a) and maximum temperature inside device (b) at V b mode. Obviously, devices do fail when the output power or the device temperature is high, e.g., when V be = 1.5 V, but devices also fail when the output power or the device temperature is low, e.g., when V be = 1.325 V. The temperature variation at failure points is up to 400 K. Therefore, device temperature is not the root cause for the failure. It should be noted that the way we define the thermal boundaries is simplified compared with the real devices that are three dimensional and have thermal dissipation paths everywhere. The 3D thermal simulations with a different tool [Reference Tao, Lee, Denis and Henderson4] showed that the peak temperature is lower by around 15%. Nevertheless, the results from our TCAD tool have no impact on the mechanism studies.
Simulated power density (a) and peak temperature in the device for two V be conditions representing two distinct regions (b).
We have seen previously that at point 1 in Fig. 3 no avalanche occurs, but why the device still fails? Figure 7 shows the self-heating effect at low current range (V be = 1.325 V). The snapback point (as denoted II) of the simulated curve without self-heating model is greater than the one (as denoted I) with self-heating model implemented by more than 6 V. In other words, the SOA boundary at low current is dominated by the self-heating mechanism. We can also see that the snapback behavior with self-heating effect is much sharper and more abrupt than that without self-heating. So the failure in this region is primarily due to the thermal effect that drives the device into an instable condition [Reference Lee, Tao and Lin7]. This is in agreement with our experimental observation.
Simulated collector current density versus collector voltage at V be of 1.325 V with (solid line) and without (dash line) self-heating model. Impact ionization model is used for both cases.
B) Constant I b mode
Figure 8 shows the simulated IV curves at constant I b mode for a 2 × 2 × 6 µm2 device. Similar to the V b mode, the current snapback can be seen and those failure points denoted as red dots form the SOA boundary. It is noted that for some curves, e.g., I b = 3E−5A, the current exhibits a very short dip following the snapback. This is probably caused by the instability around the failure point which is also numerically instable.
Simulated collector current density versus collector voltage at I b mode. Red dots indicate the failure points that form the SOA boundary.
It has been experimentally found [Reference Liu9] that for I b mode one of the two emitter fingers eventually draws most of the device current before failure, and analytical modeling [Reference Lu and Snowden16] shows that such a current “hogging” occurs when the device enters into an instable status in the real world due to the fact that two emitter fingers are not perfectly symmetrical. Now this phenomenon has been demonstrated with TCAD simulation. Figure 9 displays the current split between two fingers after certain V ce . To better understand the device operations, let us look at the 2D impact ionization and temperature before the current split (1), at the current split (2), and at the failure point (3). Figures 10 and 11 show the 2D impact ionization ratio and lattice temperature respectively at above-mentioned three conditions in Fig. 9. We can see that at point (1) both impact ionization and temperature under two fingers are quite equal, but at point (2) where the current split occurs, the physical pictures of two fingers become noticeably different. At point (3) the impact ionization under one finger is so strong that avalanche occurs, in the meantime the lattice temperature under one finger gets much hotter but the other one gets much colder. It is interestingly noted that the simulated two-emitter structure is not intentionally built to be asymmetric (see Fig. 2) in terms of physical properties and geometries, but we think there is still subtle discrepancy of the automatically generated mesh nodes between two emitters, which causes the two emitter fingers numerically asymmetric. This simulation has further demonstrated that current “hogging” effect universally exists in real multi-finger HBTs.
Simulated emitter current for each of two emitter fingers at I b = 0.1 mA. The current split occurs at point 2 and the device fail at point 3.
Simulated impact ionization ratio for two-emitter device at bias condition (1), (2), and (3) as shown in Fig. 9.
Simulated lattice temperature for two-emitter device at bias condition (1), (2), and (3) as shown in Fig. 9.
Most importantly we can observe that for I b mode, both peak impact ionization and field (not shown here) under one finger are at collector/sub-collector junction around the failure point. This demonstrates that the KIB is primarily responsible for the failure.
C) Comparison of SOA boundaries in V b and I b modes
Figure 12 plots all simulated (a) and measured (b) SOAs for I b and V b modes, respectively. The general behaviors of both simulated and measured boundaries are in good agreement. Both simulation and measurement show the boundary difference between two DC modes. This difference has been interpreted in [Reference Lee, Tao and Lin7] in which the SOA boundary of I b mode is called the secondary boundary associated with the transition region between the high-current region and low-current region of the V b mode SOA boundary. Both our measurement and simulation show that the aforementioned transition region in V b mode is actually a gap without any failure points. This gap however can be broken in for I b mode. The detailed discussion can be found in [Reference Lee, Tao and Lin7].
Simulated (a) and measured (b) SOA boundaries for a 2 × 2 × 6 µm2 device in both I b and V b modes.
IV. CONCLUSION
We performed 2D TCAD simulations to study the SOA mechanisms for InGaP/GaAs HBTs. Comprehensive physical models including hydrodynamic transport, impact ionization, and self-heating were implemented. Simulated SOA boundaries for constant V b and I b modes were qualitatively in good agreement with measurements. Failure mechanisms in different SOA regions for V b and I b modes were revealed, which also verified the analytical modeling results. This study also showed that KIB plays an important role in the failure of GaAs HBTs, which is a distinguished feature compared with Si bipolar devices. This work demonstrates that the 2D simulation by TCAD is useful not only in predicting the I–V characteristics of a device, but also in understanding why and how a device fails. It can certainly aid us in designing HBTs with better ruggedness and larger SOAs in the future.
Nick G. M. Tao received B.S. and M.S. degrees in Physics from Wuhan University of China, and Ph.D. degree in Electrical Engineering from Simon Fraser University of Canada. From 2006 to 2008 he worked on III–V HBTs and HEMTs as post-doctoral researcher in Hong Kong University of Science and Technology, and University of California, Los Angeles subsequently. Since 2008 he has been with Triquint Semiconductor, which became Qorvo in 2015, as a GaAs process development engineer. He has extensive experience in compound semiconductors, particularly in III–V RF devices and photonics. He was with Wuhan Telecommunication Device Co. of China for years working on InGaAs/InP PIN diodes and InGaAsP/InP DFB lasers. He is currently focused on the characterization and simulation of GaAs HBT and pHEMT for mobile applications. Dr. Tao is an IEEE member.
Bo-Rong Lin received the B.S. and M.S. degrees from National Chiao Tung University, Hsinchu, Taiwan in 2012 and 2014, respectively. His research activities focus on the electrothermal simulation of heterojunction bipolar transistor. He is currently a Junior Manager with China Steel Corporation, Kaohsiung, Taiwan.
Chien-Ping Lee received the B.S. degree in Physics from National Taiwan University in 1971 and the Ph.D. degree in Applied Physics from California Institute of Technology in 1978. While at Caltech, he designed and fabricated the first OEIC circuit in the world. He joined Rockwell International Science Center in 1979, and worked on GaAs integrated circuits. In 1987 he joined the National Chiao Tung University, Hsinchu, Taiwan, as a Professor and Director of the Semiconductor Research Center. Since 2004 he has also been with TriQuint Semiconductor, which became Qorvo in 2015, as a fellow engineer. His current research interests are in the areas of semiconductor nanostructures and quantum devices, III–V optoelectronic devices, MBE technology, heterostructure devices and physics, and device simulation. Dr. Lee received the Engineer of the Year Award from Rockwell in 1982 and was elected an IEEE fellow in 2000.
Tim Henderson received his Ph.D. degree at the University of Illinois at Urbana-Champaign in 1988 and is a fellow engineer and manager of GaAs process development in TriQuint which became Qorvo in 2015.
Barry Jia-Fu Lin Received BSEE from National Taiwan University, Taipei, Taiwan in 1976, MSEE from the University of Florida, Gainesville, FL in 1980, and Ph.D. degree in EECS from Princeton University, Princeton, NJ in 1985, respectively. From 1985 to 1992, he was a member of technical staff with Hewlett-Packard Laboratories, Palo Alto, CA, where he worked on GaAs pHEMT and HBT technologies for MUX/DEMUX and RFIC applications. From 1992 to 1995, he served as a director of technology for KFI Technology, Sunnyvale, CA. From 1995 to 1997, he was with Litton Solid State, Santa Clara, CA as an engineering manager for pHEMT MMIC technology for MMIC applications. From 1997 to 2004, he served as the Sr. Vice President and co-founder for EiC Corp, Fremont, CA. From 2008 till now, he has been a Sr. Director of RF amplifier product design and development for TriQuint, which became Qorvo in 2015, San Jose Design Center, responsible for product design of high efficiency high linearity PA and ultra-low noise LNAs for base-station infrastructure and WLAN access point FEM product lines.
