A) DDS-based transmitter

The transmitter architecture (Fig. 2) has been implemented for N = 4. Signal generation is carried out by DDS modules driven by the same reference clock. Each module is an AD9958 evaluation board by Analog Devices which offers two independent output channels with 200 MHz of signal bandwidth. The modules are synchronized through a software synchronization procedure managed by the PC. The controller provides control signals to the DDS boards and the trigger signal to the receiver. It has been implemented using an X3-10M board by innovative integration. This board is based on a Xilinx Spartan 3A DSP FPGA, which ensures controls flexible and fast enough to satisfy DDS maximum performances. A synchronization clock from one of the DDS boards is used as FPGA clock to produce controls synchronized to the DDS boards themselves. A PC is used to set the DDS operational mode (signal type and its specifications) and to reprogram the controller FPGA. Once the operational mode is set, signal generation by the DDS boards is managed by the controller.

Fig. 2.

Transmitter architecture.

The transmitter output signals are directly generated at IF by 10-bit digital-to-analog converters (DACs) comprised in the DDS boards hardware. The types of supported modulations are frequency, phase, and amplitude with resolutions as shown in Table 1. The device can provide different outputs: single tones, 2/4/8/16-level modulations (such as FSK, ASK, and PSK), and linear sweeps (in all the three modulations).

Table 1.

DDS modulations resolution.

The synchronization between DDS boards consists in the alignment between the synchronization clocks. Each clock is used by its own board to sample the controls which act on the output variations. Consequently, any delay between the two clocks results in a corresponding delay between the outputs. A measurement carried out on the two boards at our disposal has shown a synchronization misalignment of 240 ps. This is due to the physical differences between the two devices and can be minimized by acting on the IF output cables phases.

1) FPGA-BASED CONTROLLER

The controller FPGA ensures the capability of generating different types of signals on each channel and precise phase relationships between the channels themselves. In fact, this only involves the development of a proper control logic which, as already said, is clocked on the same timebase of the DDSs. The FPGA logic is implemented in a framework fashion: an “external” framework logic and an “inner” customizable logic (application logic). The external framework, which has been originally designed by the board producer, is realized at VHDL level. It includes all of the interfaces between the application logic and the peripherals available on the board itself (digital I/O port, analog-to-digital converters (ADCs), PCI-e interface, etc.). The application logic is created with Matlab Simulink so it ensures a functional oriented design. In this part of the logic are implemented all the structures that produce proper DDS control signals which will be output through the framework on the FPGA board digital I/O. The Matlab Simulink approach simplifies the realization of different controls required for different signal generations. Once the Simulink design of the application logic is ready, it is converted with the help of Xilinx System Generator in a netlist file that will be merged with the framework logic in Xilinx ISE to obtain the FPGA configuration file.

By default, the FPGA logic, divided in framework and application, is driven by a single clock coming from the PCI-e. In our case, the application logic has to be synchronous to the DDSs, while the framework logic must remain synchronized to the PCI-e to ensure continuous data exchange with the host PC. For this reason the FPGA logic structure has been modified, acting on the framework VHDL top-level and user constraints files, as shown in Fig. 3.

Fig. 3.

FPGA logic structure

An additional digital clock manager (a Xilinx logic primitive) has been used to manage the clock coming from the DDS. In such a way, the DDS clock drives the application logic and digital I/O, while the rest of the logic (the framework) is still driven by the PCI-e clock as default. This leads to the presence of two clock domains on the FPGA.

This implementation allows a synchronous control of the DDSs, while maintaining the other on-board peripherals still working correctly. Another important aspect of this solution is related to logic reconfigurability. In fact, simply by acting at a functional level through Matlab Simulink, it is possible to produce different control sets without writing a single line of VHDL. In the case when DDS board numbers has to be increased it is just a matter of adding other parallel control channels inside the application logic exploiting the parallel computing features of the FPGA.

B) FPGA-based receiver

A reconfigurable digital receiver based on FPGA has been already implemented for PARSAX system [Reference Wang, Krasnov, Babur, Ligthart and van der Zwan7]. Following this trend we have chosen the same system implementation for the platform receiver. This makes it possible to test the platform using PARSAX IF waveforms specifications and receiving algorithms. Moreover, the receiver has a bandwidth of 200 MHz matching the DDS-based transmitter one. In this way, the platform can benefit from a versatile receiver capable of treating different kinds of waveforms simply by changing its FPGA logic configuration. The receiver (Fig. 4) is composed of a PC and a X5-400M board by innovative integration which is an acquisition node based on ADCs and on a Xilinx Virtex 5 FPGA.

Fig. 4.

Receiver block scheme.

This architecture presents M = 2 input channels for the reference and received IF signals. The first is an IF transmitted waveform coming from the transmitter, the second is the received radar signal down-converted at IF. These two signals are digitized by ADCs and acquired by the FPGA according to the trigger signal timing. The two digitized signals are then cross-correlated inside the FPGA with a proper real-time digital signal processing algorithm. The resulting data sets are sent to a host PC, further processed and visualized in a targets range profile. Two algorithms have been already implemented and tested: the de-ramping [Reference Wang, Krasnov, Babur, Ligthart and van der Zwan7, Reference Wang, Krasnov, Ligthart and van der Zwan8] and the matched filtering [Reference Wang, Krasnov, Babur, Ligthart and van der Zwan7]. The first one is suitable for receiving LFM signals, the second is a canonic coherent receiver and is used in PARSAX for receiving PSK signals.

The use of the FPGA allows reception algorithms interchangeability. Since the algorithms implementation on the FPGA is real-time oriented the receiver is also capable of processing and visualizing real-time radar data. The number of receiving channels can be easily increased by simply parallelizing more X5 devices.

A) Simulation of two orthogonal targets using LFM signals

This simulation models the reflections from two orthogonal targets (e.g. at 8 and 12 km) using LFM waveforms. The two transmitted signals are, as in PARSAX, two LFM signals with specifications as in Table 2, one with a linear sweep up trend and the other with a linear sweep down trend. They result to be orthogonal in terms of cross-correlation [Reference Babur9]. The two transmitted waveforms and the relative delayed versions have been generated with the transmitter implementation already explained. The control signals needed to generate this waveforms set are provided by the controller FPGA which has a time base of 16 ns given by the application logic clock period. For this reason, all the delays are multiples of this time base. This also means that the minimum delay which a simulated target can assume is 16 ns. That gives a simulated target range resolution of

(1)$$\Delta R_{sim} = \displaystyle{{c \cdot 16\;ns} \over 2} = 2.4{\rm\;m}.$$

This value is lower than the de-ramping algorithm range resolution ΔR _D = 3.3m [Reference Wang, Krasnov, Ligthart and van der Zwan8] thus the targets simulation capability does not limit the overall platform resolution performance.

Table 2.

LFM signals specifications.

The measured signals spectrograms are shown in Fig. 6. The two reflected signals present respectively the delays τ_R1 = 53.3µs And τ_R2 = 80µs, given by the chosen targets distances. The spectrogram profiles, obtained by a sequence of short FFTs on a small set of local samples, show a dynamic between the sweep and the spurious frequencies of approximately 60 dB, being the sweep at −30 dB. The sweep amplitude measurement in dB has been verified by directly measuring the amplitude in mV with an oscilloscope and considering the ADC full-scale range. Instead, for an exact spurious frequencies level estimation, further and more precise measurements are necessary. However, this 60 dB is comparable to the −56 dBc of DDS spurious-free dynamic range (SFDR) in the bandwidth 100–150 MHz (as in the AD9958 datasheet), although our measurement is performed in this frequencies range instead of using the DC to Nyquist one. The spectrogram associated with the Transmitted V and Reflected 2 signals shows some artifacts that are related to a worse performance of one channel on one of the DDS boards at our disposal. This is probably related to a lower quality of its 200 MHz passive output low pass filter (implemented with discrete surface mount device (SMD) components) or to some non-linearity introduced by a defect in the DDS IC.

Fig. 6.

LFM signals measured spectrograms.

Using the de-ramping processing in reception, the range profiles with reference H or V are obtained (Fig. 7). In both profiles the desired target is correctly detected at a distance that matches the one set in the controller. The dynamic is approximately 80 dB, achieved due to the pulse compression done by the receiver. This process allows a signal-to-noise ratio (SNR) gain over the received signal SNR known as a bandwidth-time (BT) product, in this case 47 dB. The small peak represents instead the orthogonal target which is not completely rejected. Since the de-ramping algorithm implements the cross-channel interferences suppression [Reference Krasnov, Babur, Wang, Ligthart and van der Zwan1, Reference Babur9], the onset of this contribution depends on the reference signal. In fact, the coupling between the two references causes each real reference to also contain an attenuated version of the orthogonal one. In this way, de-ramping is done for both components at the same time, thus leading to the presence of two peaks.

Fig. 7.

Two orthogonal targets range profiles using LFM signals.

B) Simulation of two orthogonal targets using B-PSK signals

This simulation models two orthogonal targets (e.g. at 2 and 4 km) using B-PSK waveforms (Fig. 8) with specifications as in Table 3. Two orthogonal B-PSK signals are two signals modulated in phase with orthogonal binary sequences. In this case, for simplicity two random sequences have been chosen. To check their orthogonality, a simulation of the matched filtering processing has been carried out. It calculates the four cross-correlations given from the combinations between each reference sequence and each target sequence (obtained simply by circular shifting the relative reference one). The cross-correlation results are used to plot the four simulated range profiles (Fig. 9). When a reference is cross-correlated with its relative target, a peak at the predefined distance is present. When a reference and the orthogonal target are considered, no correlation peak is noticeable. Thus, it is possible to assume the two reference sequences as orthogonal and use them for signals generation.

Fig. 8.

B-PSK signal.

Fig. 9.

Cross-correlation simulation between orthogonal sequences.

Table 3.

B-PSK signals specifications

The matched filtering algorithm, fit to process signals with a −3 dB bandwidth B = 50 MHz, has been modified to allow the whole B-PSK signal bandwidth B = 62.5 MHz to pass. The range profiles in Fig. 10 show correct targets detections, matching simulated ones distances. The dynamic in this case is only 15 dB, so much less than when using LFM waveforms and de-ramping processing technique. This is due a 10 dB lower BT product and a received signal SNR reduction. The lower BT product is related to the fact that matched filtering real-time processing has got a higher computational cost with respect to de-ramping, thus this requires a reduction of the number of acquired samples to maintain the real-time constraint. The lower received signal SNR is due to spectral distortions and aliasing noticed in the measured spectrum (not shown here) and to the intrinsic spread spectrum nature of PSK signals. For these reasons, the orthogonal target is invisible, completely sunk into the noise floor.

Fig. 10.

Two orthogonal targets range profiles using B-PSK signals.

C) Simulation of one target using pulsed signal

A pulsed waveform can be obtained with the transmitter using the amplitude modulation mode on a single tone output of frequency f _c which acts as a carrier. The receiving algorithm is the matched filtering. A single target (e.g. at 5 km) has been simulated with a delayed version of the pulsed waveform with the specifications as in Table 4.

Table 4.

Pulsed signal specifications

A discrete Hamming function with five coefficients has been used to optimize the trade-off between frequency roll-off of the transmitted signal and reception bandwidth. In our case we want to limit the bandwidth inside the 50 MHz bandwidth of matched filtering receiving algorithm but we also want to preserve it quite large still improving the roll-off. That is why the number of coefficients is so small. This ensures a better roll-off with respect to a simple on–off modulation (rect windowing) but still a bandwidth which allows a range resolution of

(2)$$\Delta R = \displaystyle{c \over {2B}} = 8.08{\rm \;m}.$$

A measurement of the pulse carried out with the oscilloscope can be seen in Fig. 11.

Fig. 11.

Pulsed waveform time profile.

The obtained range profile is the one in Fig. 12. The detected target distance matches the set one proving that the generated pulsed waveforms can be correctly received with the matched filtering. The target peak is wider than in previous cases with approximately a −3 dB width of 5.1 m due to lower waveform resolution. Despite the lower resolution, caused by the narrower signal bandwidth, a better dynamic with respect to the B-PSK measurements can be noticed. This is probably due to the fact that narrower bandwidth and higher roll-off of the pulsed waveform spectrum provide less aliasing contributions in reception signal processing.

Fig. 12.

One target range profile using pulsed signal.