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AlGaN/GaN epitaxy and technology

Published online by Cambridge University Press:  11 March 2010

Patrick Waltereit*
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Wolfgang Bronner
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Rüdiger Quay
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Michael Dammann
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Rudolf Kiefer
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Wilfried Pletschen
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Stefan Müller
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Rolf Aidam
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Hanspeter Menner
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Lutz Kirste
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Klaus Köhler
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Michael Mikulla
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
Oliver Ambacher
Affiliation:
Fraunhofer Institute for Applied Solid State Physics, Tullastrasse 72, 79108 Freiburg, Germany.
*
Corresponding author: P. Waltereit Email: patrick.waltereit@iaf.fraunhofer.de
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Abstract

We present an overview on epitaxial growth, processing technology, device performance, and reliability of our GaN high electron mobility transistors (HEMTs) manufactured on 3- and 4-in. SiC substrates. Epitaxy and processing are optimized for both performance and reliability. We use three different gate lengths, namely 500 nm for 1–6 GHz applications, 250 nm for devices between 6 and 18 GHz, and 150 nm for higher frequencies. The developed HEMTs demonstrate excellent high-voltage stability, high power performance, and large DC to RF conversion efficiencies for all gate lengths. On large gate width devices for base station applications, an output power beyond 125 W is achieved with a power added efficiency around 60% and a linear gain around 16 dB. Reliability is tested both under DC and RF conditions with supply voltage of 50 and 30 V for 500 and 250 nm gates, respectively. DC tests on HEMT devices return a drain current change of just about 10% under IDQ conditions. Under RF stress the observed change in output power density is below 0.2 dB after more than 1000 h for both gate length technologies.

Information

Type
Original Article
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2010
Figure 0

Fig. 1. Inspection results from polarized light imaging of 3-in. SiC(0001) substrates showing a low defect density wafer (top) and a wafer having a high defect density (bottom).

Figure 1

Fig. 2. High-resolution X-ray diffraction profiles across the GaN(0002) reflection of a AlGaN/GaN heterostructure grown on a 4-in. SiC(0001) substrate by MBE. Note the excellent homogeneity as evidenced by the agreement of the profiles measured along a line at different distances R from the wafer center.

Figure 2

Fig. 3. Sheet carrier concentration of AlxGa1–xN/GaN HEMT structures grown by MOCVD (squares) and MBE (circles) on s.i. SiC substrates as a function of the Al-content in the barrier layer. Note the difference in sheet carrier concentration between MOCVD and MBE.

Figure 3

Fig. 4. Sheet resistance (Ω/sq) map of a 3-in. AlGaN/GaN HEMT wafer as determined by a contactless measurement after MOCVD growth.

Figure 4

Fig. 5. Cross-section of a metallized front to back source contact via after focused ion beam preparation. Note the excellent coverage of the via.

Figure 5

Fig. 6. Optimization of the ohmic contact annealing process: dependence of the ohmic contact resistance as a function of RTA temperature.

Figure 6

Fig. 7. Dependence of the leakage current density at 50 V drain bias (gate bias −7 V) on two different gate processes “A” and “B”.

Figure 7

Fig. 8. Load-pull mapping (continuous wave) results at 10 GHz and 30 V of 0.25 µm gate length HEMTs with 1 mm gate periphery across all 21 cells of an entire 3-in. wafer: (top) Overlay of the power sweeps and (bottom) PAE (blue), output power (red) and gain (green) of a batch of six wafers. Note the excellent homogeneity and reproducibility.

Figure 8

Fig. 9. Leakage currents (mA/mm) of a 250 nm gate length process control monitor structure at a drain bias of 150 V and a gate bias of −7 V.

Figure 9

Fig. 10. Load-pull mapping at 2 GHz and 50 V of 0.5 µm gate length HEMTs with 800 µm gate periphery across all 21 cells of an entire 3-in. wafer. Note the excellent homogeneity (top) and reproducibility (bottom).

Figure 10

Fig. 11. Load-pull measurements (2 GHz) of 0.5 µm gate length HEMTs (800 µm gate width) versus drain bias. Note that the PAE remains above 60% up to 100 V.

Figure 11

Fig. 12. Power sweep (continuous wave) of a packaged 36 mm gate width power bar at a frequency of 2.14 GHz and a drain bias of 50 V. The transistor is biased in class AB.

Figure 12

Fig. 13. Drain current change and absolute gate currents in DC reliability tests of 250 nm gates (top) and 500 nm gates (bottom). The drain current at the beginning of the test is 50 mA/mm for 500 nm gates and 150 mA/mm for 250 nm gates.

Figure 13

Fig. 14. RF reliability of 250 nm gate technology (top) at 30 V drain bias on a single stage MMIC and of the 500 nm gate technology (bottom) at 50 V drain bias on a multifinger FET.