Nomenclature

EoC

end of charge

f _cut-off

filter cut-off frequency

V _ref

voltage reference

V _shutdown

activation voltage

V _reactivation

reactivation voltage

2.0 Electrical power system architecture

Figure 1 depicts the block diagram of the Alsat-1b power subsystem. The subsystem is made up of four body-mounted solar panels with six solar array sections each, one BCM, one battery and one PCM-PDM. Each solar array portion is linked to one of the BCM’s battery charge regulators (BCRs). The main power bus, which is connected to the battery, is formed by combining all BCR outputs. During the day, each BCR manages the power from each solar array sector to correctly charge the battery based on the battery state of charge (SoC). In this setup, all available power from the solar panels is transferred to the main power bus while charging the battery and supplying the platform and payload modules.

Figure 1.

Alsat-1b power system architecture.

If the battery is fully charged and reaches end of charge (EoC) voltage, the BCRs reduce their output power to supply only the power necessary for the spacecraft/satellite. When the power available during the sunshine time is insufficient, the battery discharges to support the difference, depending on the demand from the platform and payload modules. Because no power is generated by the solar panels during the eclipse, the battery is used to meet the system’s power requirements. There are mechanical activation switches between the main power bus and the power distribution side that cut power to the distribution side during launch and allow power flow soon after orbit injection. Following the activation of the switches, the main power bus is connected to the PCM-PDM and BCM for battery voltage distribution, regulated 5V generation and generated 5V distribution. These modules also protect the power system main bus from a probable failure of one of the system’s modules. For ground and launch side operations, the power subsystem architecture includes overvoltage protection circuitry, umbilical connections and external battery charge and voltage sensor connections [Reference Bekhti, Bensaada and Beldjehem7, 8].

Figure 1 shows the Alsat-1b satellite power system architecture. The BCM converts the power required to charge a Li-ion battery and manages the main battery bus. The spacecraft loads are isolated from the battery during launch. Once separated from the launch vehicle, the activation switches automatically close. The unregulated primary battery bus powers the PCM-PDM’s power conditioning units, which create a regulated 5V supply for the telemetry and telecommand (TTC) electronics. The PCM-PDM provides power to the platform and payloads via switches and fused wires.

3.0 Power conditioning and distribution module

The PCM-PDM, as illustrated in Fig. 2, is a combination of two modules: the (PCM and the PDM. The total weight of the microtray and printed board assembly (PCA) is 1.838 kg.

Figure 2.

Alsat-1b power distribution and conditioning module.

The PCM composed of dual DC-DC flyback converters with a rating of 12.5 W, is responsible for generating the +5V bus in the power system. It has an input voltage range of 22 V to 34 V and provides power to the power subsystem CAN nodes and internal logic through the +5V bus. There are two redundant PCMs, PCMA and PCMB, that turn on simultaneously when the PCM-PDM is activated. PCMB’s output is set slightly higher than PCMA, making it the prevailing voltage. The PCM also ensures the +5V output supply is protected against under-voltage and over-voltage conditions, shutting down the system if an overvoltage occurs on the 5V line. Additionally, it protects the battery from under-voltage by shutting down at a pre-set voltage level. The under-voltage protection level is normally set to 25V, and the PCM will restart when the voltage exceeds 27V [Reference Bensaada, Mebrek and Schofield6].

The PDM section of the PCM/PDM features electronic power distribution switches and fuses to protect the power system from failures in sub-systems and payloads, as well as controlling the power distribution to maintain the system-level power budget. The PDM supplies the subsystems with both the unregulated battery voltage and the regulated +5V. The PCM-PDM serves as a buffer, transferring unregulated power from the battery/BCRs to the remainder of the spacecraft. The block diagram of the PCM-PDM is illustrated by the Fig. 3.

Figure 3.

PCM/PDM block diagram.

To prevent single point failures, redundant loads should be employed at the system level. All switches are commanded through a quad XOR gate, and redundant loads are assigned to switches on different XOR gates. Additionally, there are two battery voltage fused lines that are permanently used to power the receivers. The fuses in these lines are paralleled for redundancy purposes. The PCM-PDM has dedicated, dual, hot redundant CAN nodes that are used to control the module through software and to transmit voltage, current, status and temperature telemetry data. Each CAN node in the PCM-PDM is connected to the CAN bus and a low-level command link (LLCL), which provides a direct connection to the receivers [8].

3.1 Power conditioning unit

The power conditioning module, depicted in Fig. 4, is a flyback type DC-DC converter that is responsible for generating the +5V bus within the power system. It operates using a current mode pulse width modulation (PWM) controller IC UC2842. The main power bus serves as the input for the PCM, which then steps it down to a regulated +5V bus that supplies power to the internal logic of the power subsystem and the CAN system power buses. There are two identical hot redundant PCMs (PCMA and PCMB), both of which activate when the PCM-PDM is powered. PCMB’s output voltage has been set slightly higher than PCMA, making it the prevailing voltage with a nominal output of 5.25V (PCMB) or 5.15V (PCMA), depending on which PCM is active [Reference Rodriguez, Gonzalez and San Martin9]. During worst-case transient conditions, the +5V bus will remain between 4.5V and 5.9V.

Figure 4.

Alsat 1b power conditioning unit.

3.5 FET switch

Bipolar transistor switches are known for their inefficiency when handling larger currents. To address this issue, a new FET-based power switch has been developed, as depicted in Fig. 5. This switch operates similarly to the bipolar power switch, with the main difference being that the P channel FET is turned on (equivalent to zero volts) when the gate voltage is at a low level [Reference Williams5, Reference Bekhti, Bensaada and Beldjehem7]. On the other hand, when the gate voltage is equal to the source voltage, the FET is turned off.

Figure 5.

The FET switch.

When the output is low and the input is high, the switch is in the off state. The positive input of the comparator is maintained at approximately 3.5V by the voltage bridge divider circuit consisting of R1 and R2, making it higher than the negative input. As a result, the output stays high, keeping the FET turned off.

When the command line is at a high voltage, a 5V pulse is applied to capacitor C2, causing the negative input to become higher than the positive input. As a result, the comparator output goes low, switching the FET on. During normal operation, the negative input is slightly above the positive input, resulting in the switch being in the on state. To turn the switch off, a low-going pulse is applied to the capacitor, causing the negative input to drop below the positive input, and the switch to turn off, similar to a bipolar switch.

To determine the trip current, the voltage drop across the FET is calculated. Since the internal resistance of the FET is relatively stable, as the current increases, the voltage drop across the FET increases linearly. This increase in voltage drop leads to a decrease in both the output voltage and the voltage at the negative input of the comparator. Consequently, when the negative input drops below the positive input, the switch is turned off [Reference Bekhti, Bensaada and Beldjehem7].

The value of the select-on-test resistor R8 is adjusted to determine the trip current. By increasing the voltage drop across this resistor, the voltage on the negative input becomes higher than the positive input, resulting in an increase in the trip current. To avoid sudden changes in the input from tripping the switch, a low-pass filter is incorporated into the positive input of the comparator. This filter restricts the cut-off frequency, as defined in Equation (1).

(1) \begin{align}{f_{cut - off}} = 1/\left[2\pi \times \left( \left( {{R_{1.}}{R_2}/\!\left( {{R_1} + {R_2}} \right) + {R_3}} \right)\right. \times {C_5} \right]\end{align}

3.6 Battery voltage switches

The power conditioning module and power distribution module are designed with three distinct versions of battery voltage switches, each of which is equipped with a configurable trip setting, providing greater versatility and adaptability [8, Reference Lee12, Reference Tan13].

• 14× foldback current latch switches rated to a maximum of 2.5A (low power).

• 8× timed current latch switches rated to a maximum of 5A (medium power).

• 6× timed current latch switches rated to a maximum of 7.5A (high power).

3.6.1 Foldback current latch switch

The circuit diagram of the foldback current latch switches (FCL) is depicted in Fig. 6. The switch is activated by providing a + 5V signal to the command line. When the current exceeds the pre-set trip level, the switch will initiate current limiting. During this process, if the output voltage drops, the current limit will decrease to a low level in order to reduce FET heat generation. To restore the switch, the load must be reduced below the lower limit, and the switch must be turned off and then re-activated [Reference Kim and Kim14–Reference Bhatia, Chugh and Grewal16].

Figure 6.

28V foldback current latch switch.

3.6.2 Timed current latch switch

The circuit, as depicted in Fig. 7, features a total of eight 5A timed current latch (TCL) switches and six 10A TCL switches, along with an additional six TCL switches rated at 7.5A. Activation of the switch is achieved by driving the command line high while simultaneously pulling current through R322. If the current surpasses the established trip threshold, the switch will limit the current flow for 4 milliseconds before locking off. To reset the switch, simply toggle it off and then on again [Reference Lee17–Reference Wang and Liu19].

Figure 7.

28V timed current latch switch.

3.9 Grounding and isolation scheme

The objective of the SSTL power grounding and isolation technique is to eliminate DC ground loops and reduce AC disturbances among bus users. This is achieved by minimising the total main ripple currents that flow through shared return pathways and structures. The method has been successfully implemented on previous SSTL small spacecraft in low Earth orbit (LEO) and medium Earth orbit (MEO). The entire power system was designed with the assumption that the grounding policy outlined in Fig. 8 would be incorporated into the spacecraft design [Reference Du and Yin20–22].

Figure 8.

Grounding scheme [8].

The power system is composed of two main electronic modules: the BCR and the PCM-PDM, along with the solar arrays and battery that complete the system. The spacecraft star point, which is a central location where the unit-level ground planes or return lines are electrically connected to the spacecraft structure, is situated within the BCR. Currently, the star point is housed in the BCM for grounding purposes. However, if needed, the star point can be relocated to the PCM/PDM to meet specific requirements [Reference Boncyk23].

The PCM-PDM is connected to the BCR ground plane by bypassing the local star point, as depicted in Fig. 9. The negative battery connection is also linked to the BCR through the battery arm plug (-Ve safe arm). The BCR and PCM-PDM provide switched lines to all other modules and equipment on the spacecraft, with the BCR supplying unregulated 28V switches and the PCM-PDM offering both unregulated 28V switches and 5V regulated switches. Each switched line is accompanied by a corresponding ground line, which grounds the module ground plane for non-isolated modules or the return line for isolated modules, depending on the chosen isolation scheme [8, Reference Liu and Liu24].

Figure 9.

Power system grounding diagram.

4.0 Module tests

The PCM-PDM test is a crucial step in ensuring the reliability and performance of the module. This test evaluates the module’s ability to control and distribute power from the solar arrays and battery to the rest of the spacecraft. The test procedure typically involves a series of electrical and functional tests, including input/output voltage and current measurements, as well as testing of the protection circuits and fault management strategies. In addition, the performance of the module’s telemetry system, which is responsible for transmitting data and commands, is also assessed. The PCM-PDM test is critical in verifying that the module meets the design specifications and requirements, and that it is ready for integration with the rest of the spacecraft subsystems. The tests performed are organised into the following categories:

1. 1. In order to eliminate infant mortalities before system level testing, it is imperative to subject all modules to a burn-in test to ensure they accumulate a total on-time exceeding 168 hours (equivalent to seven days). The burn-in test must be completed prior to the system thermal vacuum testing to guarantee reliable and optimal performance.

2. 2. The first step in integrating the various sub-systems of the platform involves assembling them in a soft stack configuration. Each module undergoes individual testing in the laboratory before being integrated into the satellite structure for comprehensive testing. Modules and the battery are flexibly assembled on a table using the designed harness, forming what we refer to as a soft stack. This approach facilitates testing of the entire system. In the event of a subsystem anomaly, disassembly is unnecessary, mitigating any associated risks or accidents. This step aims to verify the interconnection of the modules and test their functionalities. This is made possible by the modularity of the SSTL platforms, which consist of several electronics boxes that are mounted together to create the core stack. To facilitate the integration process, module boxes are positioned on their sides within integration stands and secured using integration clamps. This straightforward approach minimises the effort required to remove individual units in case any issues arise during the integration process. Figure 10 illustrates of this approach to initial module integration. The aim of this initial module integration is to conduct initial checks on each of the individually tested modules to verify that each one fits and functions with the harness. Power, grounding and isolation is checked on each module, and harness power checks are performed prior to module connections to confirm voltage level and polarity. Once this has been completed, the module will be electrically connected; at this stage modules and flight harness connectors will use connector savers. The main advantage of this framework is that a module can be easily inserted and taken out if required, irrespective of its position in the stack. If the module works with the power system and telemetry can be obtained, then the module can be integrated regardless of whether certain other modules are present or not.

3. 3. The last step in the platform assembly process involves the final platform hard stack procedure, this implies that all modules are assembled within the satellite structure to undergo rigorous environmental testing as shown in Fig. 11, which encompasses assembling the complete platform into its designated flight configuration. This includes ensuring that the platform fixings are tightened to their appropriate torque levels and that the flight harness is connected to modules with the connector savers removed. Additionally, the propulsion subsystem is integrated into the spacecraft during this process. It is crucial to note that even in this fully assembled configuration, the spacecraft can be disassembled seamlessly if any issues arise during functional testing.

4. 4. The objective of conducting platform ambient pressure thermal cycle tests is to evaluate the spacecraft’s performance across a broad temperature range, typically ranging from −20ºC to +50 ºC. The test procedure includes at least one round of thermal cycles, consisting of three hot/cold cycles. The tests assess the power consumption levels, interfaces and overall functionality of the platform under various temperature conditions. Furthermore, the cold start of the platform is performed to assess the efficiency of battery charging and power regulation, as well as the RF system’s bit error rate and TTC functions. The tests also involve evaluating the robustness of cross-strapped interfaces and redundant data bus (CAN bus). So, to verify the functionality of the platform’s electrical interfaces in the flight configuration under varying temperatures, an ambient pressure thermal cycle campaign is conducted. Each module must undergo a minimum of one round of thermal cycling, which comprises three cycles of hot and cold temperatures. However, some modules may undergo more than one round of thermal cycling based on the schedule. This process as shown in Fig. 12, ensures the robustness of the platform’s electrical interfaces, guaranteeing their stable operation under extreme conditions.

5. 5. When significant hardware changes are made, the units are subjected to unit level qualification vibration tests to ensure their reliability (see Fig. 13). The unit is subjected to qualification loads that simulate the expected launch environment for the particular unit. Typically, the tests involve both random vibration and sine sweep. For generic hardware units, a more generalised spectrum is used to cover a wider range of launch environments. By conducting these tests, the unit’s capability to withstand the harsh launch conditions is verified, ensuring that it operates safely and effectively during the launch phase. obviously, a functionality test is carried out both prior to and subsequent to the vibration test. This is done to confirm that the unit is operating correctly and effectively, both before and after being exposed to the vibration test. This process helps to identify any issues or anomalies that may have arisen due to the vibration test, and ensure the unit’s reliability and functionality under normal operating conditions. By conducting these tests, the unit’s ability to perform its intended functions is verified (pre/post vibration module test), which is crucial to its successful operation. The satellite undergoes a comprehensive vibration qualification test campaign, encompassing modal, sine sweep and random vibration tests. Notably, the initial frequency of the satellite is 68 Hz, meeting the launcher’s requirements. Furthermore, all modules and the satellite itself successfully endure random and sine sweep vibrations, with amplitudes ranging from 0 to 2000 Hz falling within the qualification envelope of each module. No damage was observed in the satellite structure throughout these tests.

6. 6. The EMC test campaign as shown by Fig. 14 serves a critical purpose in verifying the spacecraft’s compatibility with the launch vehicle, minimising the likelihood of incompatibilities that may lead to severe mission delays or the loss of a launch opportunity. Moreover, as a secondary objective, the campaign also validates the functionality of the spacecraft systems in their flight configuration, further reducing the risk of system malfunctions during launch and operation. By fulfilling both these objectives, the EMC test campaign plays an essential role in ensuring the success of the spacecraft launch and mission.

Figure 10.

Soft stack configuration and test.

Figure 11.

Hard stack configuration and test.

Figure 12.

Alsat-1B in thermal cycle test chamber.

Figure 13.

Alsat-1B vibration tests.

Figure 14.

Alsat-1B in EMC test chamber.

The full set of tests performed cover:

• Radiated emissions (launcher and range compatibility)

• Radiated susceptibility (launcher and range compatibility)

• Spacecraft self-susceptibility tests (under various predefined operational modes)

• Spacecraft antenna functional checks

• Payload compatibility

• Spacecraft wireless operation (end to end testing)

1. 7. The main aim of the thermal vacuum testing (TVT) test is not to replicate the space environment during different mission phases. Instead, its primary goal is to confirm the spacecraft’s performance under high vacuum conditions and extreme temperatures, both hot and cold. To achieve this, a balance is maintained to subject the spacecraft to sufficient thermal stress to reveal any potential design or manufacturing weaknesses, while ensuring that flight hardware is not over-stressed. In doing so, the testing indirectly validates the effectiveness of the spacecraft’s thermal design (see Fig. 15) by verifying elements of the thermal model used in its construction. The test methodology involves cycling the shroud and base plate repeatedly between the required temperature extremes, as many times as possible within the test campaign’s allotted time frame. Simultaneously, the electrical operation of every subsystem and payload is tested to ensure their proper functioning. Specifically, the capability to switch on and off systems under both hot and cold temperature conditions must be validated.

2. 8. The aim of the thermal cycle control is to allow each unit to be tested (see Fig. 16) at its desired temperature without allowing other units to go beyond their limits. In practice this is likely to mean that not all units will be tested at the full extremes of +50°C to −20°C, in this case the tests will be carried out at the widest temperature range possible and must be inside the boundary set by the operational predictions, However, it is crucial to note that the spacecraft battery should only be charged between 0°C and +30°C, and this parameter must be strictly adhered to during the testing.

3. 9. The checkout procedure at the launch site for the AlSat-1b spacecraft is crucial. Given the constraints of time, it becomes challenging to conduct comprehensive electrical tests for all the spacecraft hardware. Therefore, this step must be executed meticulously to ensure the spacecraft’s readiness for launch. The purpose of this test procedure is to:

   • Visually confirm that spacecraft have not been damaged during transportation to the launch site.

   • Set up the electronic ground support equipment (EGSE) racks ready for launch site testing.

   • Perform battery checkout and storage recovery and charging of the flight battery.

   • Conduct baseline functional tests of spacecraft modules.

   • Conduct limited and payload interface testing.

   • Implement red tag/green tag item installation and removal and solar array functionality.

   • Perform propulsion system filling.

Figure 15.

Alsat-1B in TVT test chamber.

Figure 16.

PCM-PDM temperature in TVT test chamber.

4.1 Grounding and isolation scheme

The PCM is the first component of the PCM-PDM that must be operational for the testing process to proceed. This is because the 5V line generated by the PCM is responsible for powering the electronics and logic used in the power system, making it essential for conducting further tests. The PCM has two redundant modules, A and B, with B set to a higher voltage level to take over in the event that both are activated. A block schematic of the PCM electronics is shown in Fig. 17.

The first stage of the testing procedure involves determining the switching frequency of the PCM. This step evaluates the operating frequency of each power conditioning module to confirm that it conforms to the established standards, and examines the precision of the internal voltage reference in the pulse width modulation integrated circuit (PWM IC). The outcome of these assessments are documented and presented in a comprehensive manner in Table 1.

Figure 17.

PCM electronics.

Table 1.

PCM operating frequency and voltage reference

The PCMs begin operating once the supply voltage is applied to the PWM ICs (UC2842). A waveform is generated in the auxiliary winding of the PCM inductor, which is then rectified, producing a DC voltage of 16.1V for PCM A and 16.62V for PCM B (as depicted in Fig. 18). The higher voltage of PCM B allows it to supply power to the UC2842 after start-up.

Figure 18.

PCM Aux-winding waveform.

At the start-up of the PCM, an overshoot is observed on the 5V line. This overshoot can cause the PCM to shut down immediately after being turned on if it exceeds a certain limit. Figure 19 illustrates this phenomenon, where the peak voltage reached 5.925V and the time between PCM A and B turning on was approximately 65µs. It is important to ensure that the overshoot on the 5V line remains within acceptable limits to prevent the PCM from tripping off.

Figure 19.

PCM start-up waveform for different temperature.

The traces of the flyback MosFET gate and drain are shown in Fig. 20. The peak gate voltage measured was 16.93V for PCM A and 17.18V for PCM B, which is within the acceptable range of 12–18V. The measured ripple voltage was approximately 15mV for PCM A and 16mV for PCM B, which is well below the acceptable limit of 100mV.

Figure 20.

PCM gate and drain waveforms.

The PCMs also feature an automated under-voltage cut-off function, which automatically turns off the PCM if the battery voltage drops below a predetermined level. This helps to ensure that the battery voltage does not fall to an unrecoverable level and prevent it from being subjected to excessive strain. The PCM’s reactivation voltage is approximately 2V higher than the shutdown voltage, which creates a hysteresis effect. This helps to prevent the PCM from rapidly switching between the on and off states and allows the battery to recharge. The test results of this function can be found in Table 2.

Table 2.

PCM battery voltage shutdown/restart

The PCMs are designed to function as hot redundant switchovers. The testing procedure involves simulating an over-voltage condition on each PCM output, which causes the affected PCM to turn off and triggers a switchover to the other PCM. The complete switchover waveform is depicted in Fig. 21, and a zoomed-in version of the waveform provides a closer look at the voltage levels during the initial transients.

Figure 21.

PCM switchover transient waveform.

The PCMs have a maximum rated output current of 2.5A, and it is important to ensure that this limit is not exceeded. Testing should be performed at various input voltages of 22V (best case), 28V (nominal case) and 34V (worst case) for each PCM combination, including PCMA only, PCMB only and PCMA + B. The efficiency of the PCMs for each scenario is represented in Fig. 22.

Figure 22.

PCM efficiency at minimum and maximum voltage.

In addition to the previous tests, a simulation test is carried out to examine the PCM’s response to an overload situation and to verify that the 5V line stays within the specified parameters. The results of this test, including all possible cases and the minimum and maximum voltage, are presented in Fig. 23.

Figure 23.

PCM overload.

The integration of the PCM has enabled the removal of the need for a separate 5V external power supply. The CAN bus is now powered directly from the PCM. It is important to verify that telemetry data is received on both nodes of the CAN network. Additionally, the power consumption of the system should be measured, as outlined in Fig. 24. This will provide valuable insights into the performance of the PCM and the overall efficiency of the system.

Figure 24.

Telemetry check on CAN nodes.

4.2 Power distribution unit

The PDM serves an important role in power distribution from both the PCM and battery to the subsystems. It provides crucial circuit protection by using a combination of resettable circuit breakers and fused lines to ensure the safe and reliable supply of power to the receivers and power system.

4.2.1 TCL switches

The TCL switches require two key measurements to be made to ensure their proper function: the inrush capability of the switch and the trip current level. To assess the inrush capability, a capacitive load response test is conducted to ensure the switch can provide the expected inrush current at switch-on. The switch should remain on, and the current drawn should decrease to zero once the capacitor has fully charged. During the tests, the voltage across the capacitor and the current from the switch to the capacitor are recorded and captured in the oscilloscope waveforms shown in Fig. 25. This test is repeated for all TCL switches.

Figure 25.

TCL switch capacitive load response waveform.

To properly evaluate the TCL switches, two measurements must be made: the inrush capability and the trip current level. The capacitive load response of the switch is tested to verify its ability to provide the expected current inrush during switch-on. The switch should remain on until the capacitor is fully charged and the current drawn should drop to zero. The test results, including the oscilloscope waveforms of voltage across the capacitor and current from the switch to the capacitor, are depicted in Fig. 25 and are repeated for all TCL switches. It’s important to note that a resistive load should never be used to test the trip setting on TCL switches. The oscilloscope waveforms of voltage across the trip resistor and current from the switch to the trip resistor are recorded and shown in Fig. 26 for all TCL switches.

Figure 26.

TCL switch resistive load response waveform: (a) ambient, (b) cold and (c) hot temperature.

Flow in response to overloading conditions, whether caused by resistive loads such as heating elements or by capacitive loads, such as motors and power supplies. This ability to handle a diverse range of loads is a key feature of TCL switches, ensuring reliable and safe performance in a variety of applications (see Fig. 27).

Figure 27.

TCL switch capacitive and resistive load trip current.

4.2.2 FCL switches

The input voltage for the test is set to a minimum of 24V, with the current limit set to 20% above the switch’s trip setting. The test is also performed with a maximum input voltage of 34V. If the current ever surpasses the trip level, the TCL switch will initiate current limiting to protect against overloading. During this process, if the output voltage drops, the current limit will automatically adjust to a lower level, minimising dissipation in the FET. The recorded trip current results are depicted in Fig. 28, providing a clear representation of the switch’s performance.

Figure 28.

FCL switch trip current.

4.2.3 5V FET switches

The test procedure included capturing waveforms to demonstrate the stability of the 5V line for the four switches used (SW4, SW5, SW7 and SW9). The waveform of switch four (SW4) is shown in Fig. 29. It is crucial that both PCMs are kept in the on state throughout the test, as this will provide accurate and meaningful results. The waveform recordings provide valuable information about the stability of the 5V line and the performance of each switch, allowing for a thorough analysis and assessment of the system’s capabilities.

Figure 29.

5V FET switch waveform.

The waveforms of the 5V FET switches were analysed to determine the maximum and minimum voltage levels of the PCMs at the point when the switch trips to the off state. This data is depicted in Fig. 30, providing a clear visual representation of the voltage levels during the tripping process. By recording the PCM voltages during switch tripping, it is possible to gain valuable insights into the stability and performance of the system, and identify any potential areas for improvement.

Figure 30.

5V FET switches minimum/maximum voltage and trip current.

To enhance the understanding of the PCM-PDM module’s functionality, we’ve incorporated a Fig. 31 showcasing its interaction with other subsystems through various switches. Additionally, this figure displays the last telemetry (TLM) data collected during the module’s operation in space, providing valuable insights into its performance in real-world conditions.

Figure 31.

PCM-PDM switches state in nominal mode.

During nominal mode, when no imaging or transmission operations occur, most subsystems are deactivated (see Fig. 31), with switches set to the off state. However, essential subsystems, such as the on-board computer (OBC) and reaction wheels, remain activated to ensure the satellite’s basic functionality.

During imaging-downlink mode, the majority of subsystems are activated by toggling the dedicated switches of the PCM-PDM module to the on state, ensuring precise satellite pointing and stability throughout the operation. Figure 32 visually demonstrates the activation of all attitude and orbit control system (AOCS), payload and X band transmitter (xTx) equipments. Given the substantial power consumption involved, the battery discharge is warranted to support this operation.

Figure 32.

PCM-PDM switches state in imaging-downlink mode.