I. INTRODUCTION
The growing demand for higher data rates in wireless transmission motivates the interest of the engineering research community in multi-Gbps wireless transceivers. The wide bandwidth required for such high data rates is currently available at 60 GHz, where up to 7 GHz of unlicensed band can be used. In this context, the design of 60 GHz building blocks suitable for integration in systems-on-chip is subject of research. One specific challenge related to the implementation of the PLL is the integration of loop filters (LFs). In [Reference Winkler, Borngräber, Heinemann and Herzel1–Reference Lee, Kim and Yu4] several millimeter-wave fully integrated PLLs were presented. These PLLs use on chip Metal-insulator-metal (MIM) or Metal-oxide-semiconductor (MOS) capacitors for the LF and a small loop bandwidth to optimize phase noise while sacrificing the system dynamic behavior. In this work, we discuss the use of capacitor multipliers for the integration of the PLL. In contrast to the other PLLs, the system was optimized for very fast settling time. Additionally, we investigate the impact of the capacitor multiplier on the phase noise of the PLL.
Figure 1 shows the system-level schematic of the transmitter, which relies on the PLL presented in this work. The direct up-conversion architecture was adopted. The transmitter consists of an Field programmable gate array (FPGA) that feeds two independent data streams into the in-phase (I) and quadrature (Q) paths of the analog frontend through an FPGA interfacing circuit. The I and Q data are up-converted to the 60 GHz band using an I/Q modulator and then fed into a wide-band power amplifier, which feeds the signal to the antenna. Since the target system is a transceiver operating in a time-division duplexing mode, the transmitter will continuously have to be switched on and off. In order to sustain the required effective data rate in switching mode, the PLL should be able to settle in a very fast time; a settling time of 4 µs was specified to be sufficient from the system requirements. In this context, the loop bandwidth is a crucial system parameter as it affects both settling time and phase noise, and defines the trade-off between them. But, because the receiver is using a carrier recovery circuit that can follow the slow changes in carrier such as phase noise, the phase noise performance could be sacrificed and the loop bandwidth was increased until the required settling time was achieved.
Transmitter architecture.
II. SYSTEM ARCHITECTURE AND SIMULATION
The integer-N synthesizer architecture, as shown in Fig. 2, was adopted due to its lower risk and suitability for the required application. A common collector Colpitts voltage controlled oscillator (VCO) was used in a PLL system to generate the 61.44 GHz carrier. The VCO was followed by an output splitter that feeds the output of the VCO into two paths; one was used for the frequency divider and the other was used to drive the I/Q modulator. The frequency divider divides the 61.44 GHz signal to 60 MHz (the frequency of the crystal oscillator). The output of the divider was then fed into a conventional tri-state phase frequency detector (PFD), optimized to minimize the dead zone. The output of the PFD was used to drive a highly matched charge pump (CP), which, with such matching, minimizes the power of the spurs generated around the carrier and reduces the noise generated by the CP transistors. Finally, the output of the CP was connected to a second-order integrated LF. The approach of capacitor multiplying was used to enable the integration of the LF on the same chip. System simulations were used to optimize the filter parameters and resolve the trade-off between the loop dynamics, stability, spur power, and phase noise performance. Figure 3 shows the trade-off between loop bandwidth, phase noise, and settling time for three different loop bandwidths.
Synthesizer linear model with noise sources.
Loop bandwidth versus (a) phase noise and (b) settling time.
A) Dynamic behavior
The following parameters of the different blocks of the PLL were used for system simulations: the PFD/CP gain (K PFD) = I CP = 230 µA, the VCO gain (K VCO) = 2 × π × 5 Grad/V, the division ratio (N) = 1024, and a second-order LF. The system was modeled using Verilog-A and simulated for its locking dynamics; the LF parameters were chosen to give the optimum loop bandwidth and settling time. The loop bandwidth was chosen to be 1.6 MHz to enable the PLL to be as fast as required.
B) Phase noise simulations
The model shown in Fig. 2 can be used to predict the PLL's phase noise performance. The different transfer functions of the different noise sources can be derived, as shown in Table 1, and then the noise spectrum of each block can be simulated and shaped to the output using its own transfer function, as described in [Reference Kundert5]. In an integer-N synthesizer, the noise of the PFD/CP combination is the dominant part [Reference Rogers, Plett and Dai6]. In this case, due to the integration of the LF, the LF also highly contributes to the PLL phase noise. The noise of the PFD/CP, VCO, and the LF were simulated and shaped to the output. The result is shown in Fig. 4; the measured spectrum closely matches its simulation.
SSB phase noise (a) with capacitor multiplier measured versus simulated and (b) without capacitor multiplier simulated.
Noise and loop transfer functions [Reference Kundert5].
In order to investigate the effect of the capacitor multiplier on the phase noise of the system, the loop was simulated assuming a conventional filter with no capacitor multiplication and the simulation results were compared. The effect of using the capacitor multiplier has shown a degradation of around 5 dB on the phase noise inside the loop bandwidth, as shown in Fig. 4.
III. CIRCUIT DESIGN
A) VCO
The common collector Colpitts oscillator is well known for its good phase noise performance at high frequencies. As a result, it was adopted for this system. Design and characterization of this VCO were presented in [Reference Barghouthi and Ellinger7].
B) Divider
The divider is used to generate a 60 MHz signal, which is suitable for comparison with the 60 MHz crystal oscillator output, from the 61.44 GHz VCO output. The division ratio of 1024 was implemented by cascading ten divide-by-two static divider stages. The split-load architecture was adopted for the latch used in the static dividers [Reference Lee, Lee, Hsiao, Huang and Chen8]. The bias current and the resistors ratio were scaled to optimize the self-oscillation frequency of each divider stage. By doing this, each stage requires minimum input power and the output power of the previous stage can be scaled down, which finally results in lower power consumption. The output spectrum of the 1024 divider is shown in Fig. 5.
The output spectrum of the 1024 divider at 61.44 GHz input frequency (60 MHz output).
C) Phase frequency detector
A conventional tri-state PFD, which uses two edge-triggered flip flops and an AND gate with a delay in the reset path to minimize the dead zone of the PFD, was used [Reference Rogers, Plett and Dai6].
D) Charge pump
The role of the CP is to convert the phase difference between the high-quality crystal oscillator signal and the output of the divider into a linearly proportional average current, which is injected into the LF and corrects for phase and frequency differences between the reference crystal and the divider output. The phase noise and the power in the spurs around the carrier directly benefit from improvements in the matching between the up and down currents of the CP [Reference Rogers, Plett and Dai6]. The highly matched CP architecture, shown in Fig. 6, was adopted. This architecture uses a feedback structure to minimize the effect of channel length modulation on the mismatch between the up and down currents.
Highly matched CP architecture [Reference Rogers, Plett and Dai6].
E) Loop filter
The LF converts the output current of the CP into a voltage, which drives the loop into locking. The second-order LF architecture is shown in Fig. 7. The large capacitance of the filter was generated by capacitor multipliers in order to enable its integration on chip. The capacitor multiplier in [Reference Hwang9], as shown in Fig. 8, was adopted for that purpose. In Fig. 9, a comparison between the input impedance of the conventional LF versus the input impedance of the LF using the capacitor multiplier is shown. The synthesizer loop was simulated using the conventional loop filter (LF) and the LF using the capacitor multiplier: the dynamic behavior shown in Fig. 10 was obtained. The two LFs show very similar performance and a fast settling time of 4 µs.
Second-order LF (a) without and (b) with capacitor multiplier.
Capacitor multiplier [9].
Simulated impedance of the conventional LF versus LF using capacitor multiplier: (a) magnitude response and (b) phase response.
Simulated dynamic behavior: (a) conventional LF and (b) LF with capacitor multiplier.
F) Output splitter
The output of the VCO is fed into the input of the output splitter and two output signals are generated. One is used to drive the divider and should supply the divider with the required power for the appropriate operation. A matching network was designed to guarantee such power level. The other output of the splitter is matched to supply the mixer with −7 dBm of differential power, which is required for its optimal functionality.
IV. CIRCUIT CHARACTERIZATION
The layout of the synthesizer was designed to enable the testing of the individual high-frequency blocks used in wafer measurement. Figure 11 shows a photo of the fabricated IC. For testing the closed-loop system, a printed circuit board (PCB) was designed to generate the DC bias voltages and currents for the synthesizer; the chip was wire-bonded. The output of the synthesizer was measured using an on-wafer probe, which also helped to provide one of the outputs with 50 Ω termination. The measured spectrum is shown in Fig. 12.
Synthesizer chip photo.
Measured output spectrum: (a) spurs and (b) phase noise.
In Table 2, a comparison with state-of-the-art PLLs is shown. The table shows that the loop bandwidth used in this work is much larger than in other presented PLLs. This is the controlled result of a design choice dictated by the transmitter specification: the loop bandwidth was increased to achieve required settling time, taking into consideration the low sensitivity of the bit error rate at the receiver end to phase noise, due to using a carrier recovery circuit. This is the result of a trade-off involving phase noise, loop bandwidth and settling time, presented and discussed above. It was also predicted by the system simulations. For a fair comparison between different designs, the loop noise can be normalized by the division ratio (N) as this linearly amplifies the noise to the output. With this assumption, a new figure of merit (FOM) can be defined by referring all PLLs to a loop bandwidth of 1 MHz assuming roll-off behavior of 20 dB/decade for the loop; this is an upper boundary performance as 20 dB/decade is the minimum slop possible. The FOM allows the comparison of different loops with different bandwidths. The FOM is defined as:
where f offset is the offset frequency at which phase noise is calculated, PN is the phase noise at the given offset frequency and f BW is the loop bandwidth.
Comparison with state-of-the-art synthesizers.
The use of the PLL was demonstrated successfully by including it in the system and transmitting a BPSK data stream at a rate of 3.75 Gbps and receiving it error free.
V. CONCLUSION
The design of a 61.44 GHz fully integrated PLL that uses the approach of capacitor multiplying for the integration of the LF was presented. The expected degradation of the phase noise performance due to the capacitor multiplier compared to MIM capacitors was simulated: the phase noise system simulations have shown very close matching with the measured spectrum. The PLL was optimized for a very fast settling time of 4 µs, by setting the loop bandwidth at 1.6 MHz. The measured phase noise at 1 MHz offset frequency is −71 dBc/Hz. In case better phase noise is required for higher-end applications, an improvement of around 5 dB can be achieved by replacing the capacitor multiplier with MIM capacitors at the cost of more LF area. In addition, the loop bandwidth can be decreased, at expenses of system dynamics.
ACKNOWLEDGEMENTS
This work was supported by the German Ministry of Education and Research in the framework of project “Enablers for Ambient Systems, part A” (EASY-A). PCB Layout software tools were partly funded by Altium.
Atheer Barghouthi received his B.Sc. in electrical engineering in 2004 from Birzeit University in Palestine with distinction and received his M.Sc. in microelectronics and microsystems from Hamburg University of Technology in 2008 with distinction. Currently, he works for his Ph.D. as a scientific research employee in Dresden University of technology in the field of RF circuit design.
Marcus Hellfeld received the Dipl.-Ing. degree in electrical engineering from the Technical University of Dresden in 2005 with honor. From 2005 to 2008, he investigated event driven continuous dynamical systems. In 2008, he changed to 60 GHz circuits. His current research interest is analog-oriented circuits design for signal processing directly in the 60 GHz domain. Currently, he is working toward his Ph.D. as a scientific research employee in Dresden University of technology in the field of RF circuit design.
Corrado Carta was born in Cagliari, Italy. He received the Master degree in electrical engineering from the University of Cagliari, Italy, in 2000 and the Ph.D. degree from the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, in 2006. From July 2000 to February 2006, he was with the Microwave Electronics Group of ETH Zurich, where his main research interests were in the field of silicon-based RFIC design for wireless communications. From April 2006 to May 2008, he was with the High-Speed Electronics Group at the Electrical and Computer Engineering Department of the University of California, Santa Barbara, where his research work focused on the design of silicon-based integrated circuits for very large mm-wave phased arrays. In June 2008, he joined Sonos, Inc., where he led the RF and compliance team, involved in the development and characterization of the wireless interface of new and existing products. In March 2010, he joined the Chair for Circuit Design and Network Theory at TU Dresden, where he is currently leading the mm-wave IC design group.
Frank Ellinger was born in Friedrichshafen, Germany, in 1972. In electrical engineering (EE), he graduated in 1996 from the University of Ulm, Germany. He received an MBA and a Ph.D. degree in EE from the ETH Zürich (ETHZ), Switzerland, in 2001, and the habilitation degree in high-frequency circuit design from the ETHZ in 2004. Since August 2006, he is full professor and head of the Chair for Circuit Design and Network Theory at the Dresden University of Technology, Germany. Currently, he is a member of the management board and coordinator of the communications area in the German excellence cluster project Cool Silicon. From 2001 to 2006, he was head of the RFIC design group of the Electronics Laboratory at the ETHZ, and a project leader of the IBM/ETHZ Competence Center for Advanced Silicon Electronics hosted at IBM Research in Rüschlikon. Professor Ellinger has been coordinator of the EU-funded projects RESOLUTION and MIMAX. He published more than 170 refereed scientific papers, most of them IEEE journal contributions, and 3 patents. Professor Ellinger authored the lecture book “Radio Frequency Integrated Circuits and Technologies” published by Springer. He was elected by the IEEE MTT S as IEEE Distinguished Microwave Lecturer for 2009–2011.
