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A new methodology for optimal RF DFT sensor design

Published online by Cambridge University Press:  03 July 2012

Conrado K. Mesadri
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Aziz Doukkali
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Philippe Descamps*
Affiliation:
LaMIPS, Laboratoire Commun CRISMAT-NXP Semiconductors-PRESTO Engineering, UMR 6508 CNRS, 6 Boulevard Maréchal Juin, Caen, France. Phone: + 33 231 456 029
Christophe Kelma
Affiliation:
NXP Semiconductors, 2 Esplanade Anton Philips, Campus Effiscience, Colombelles BP 20000, Caen 14096, Cedex 9, France
*
Corresponding author: P. Descamps Email: philippe.descamps-lamips@nxp.com
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Abstract

In this paper, a new methodology to compare the robustness of sensor structures employed in radiofrequency design for test (RF DFT) architectures for RF integrated circuits (ICs) is proposed. First, the yield loss and defect level of the test technique is evaluated using a statistical model of the Circuit under Test (obtained through non-parametric statistics and copula theory). Then, by carrying out the dispersion analysis of the sensor architecture, a figure of merit is established. This methodology reduces the number of iterations in the design flow of RF DFT sensors and makes it possible to evaluate process dispersion. The case study is a SiGe:C BiCMOS LNA tested by a single-probe measurement.

Information

Type
Research Papers
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012
Figure 0

Fig. 1. LNA circuit schematic.

Figure 1

Fig. 2. Ideal measurement simulation schematic.

Figure 2

Fig. 3. KDE procedure example.

Figure 3

Fig. 4. Scatter plot of Vp and NF of the original sample (blue circles) and of a recreated sample of the same size (red triangles).

Figure 4

Fig. 5. RF DFT sensor measurement simulation schematic.

Figure 5

Fig. 6. Measurement quality schematic.

Figure 6

Table 1. Di,s, Freji,s, Dpassi,s, and Tlimi,s (for N = 106).

Figure 7

Fig. 7. Defective circuits, yield losses, and defect levels for both measurements.

Figure 8

Fig. 8. $\tilde F$ function distribution of our case-study (example).

Figure 9

Fig. 9. Normalized yield loss and defect level with respect to Fm.

Figure 10

Fig. 10. Alternative figure of merit simulation schematic.