Motivation for the study

Highly precise RF frequency sources are in great demand for PDRF sensor applications. In recent times, higher end RF spectrum have been encouraged to utilize in the field of sensor design for its linked advantages. Advantage of miniaturized size and enhanced resolution capabilities can be realized through sensors operating at higher frequencies. Piezoelectric material-based crystal oscillator offers ultra-low switching time making PLL a preferred choice. Similarly, DR exhibit a high Q-factor, making preferred choice for generating ultra-low phase noise signal. The above cited features make crystal based PLL source (direct or multiplier-based approach) and DRO as an obvious choice. It is desired to develop an advanced frequency source without sophisticated design procedure. Phase noise performance of frequency source under RVs is crucial for its practical utilization. In line with this context, the purpose of the proposed work is to develop a unique design technique and procedure for ultra-low phase noise frequency source and its validation under ambient environment.

Phase noise in RF sensor and its acceleration sensitivity

In an airborne PDRF sensor, the preventive factor in identifying and tracking a slow-moving targets known as “tail chase” mode operation is not only clutter but the oscillator’s flicker noise commonly known as phase noise. Phase noise in a PDRF sensor occurs due to spectrum impurity in the transmitted signal and in receiver side due to LO instabilities. These instabilities limit the RF sensor achievable angular accuracy in any direction-finding technique (due to increase in noise floor). In general, resolution is the smallest separation necessary to declare two targets present apart in range (ΔR), Doppler (Δf), and angular position (Δθ). Phase noise of the LO decides the lowest detectable signal strength reflected from the target of interest. The overall detection dynamic range of the RF sensor gets influenced by the noise of the transmitted signal. Thus, it is not only important to know the absolute noise of the distinct oscillators but also to consider the additive noise from inline devices like amplifier, mixer, pulse modulators, etc. As transmitted signal in PDRF sensor is pulsed, it demands absolute phase noise measurements of the pulsed carrier to quantify the overall performance of the system. The low-frequency flicker noise or pink noise rides around spectral line at fundamental tone (${f_0}$). Fundamental carrier (${f_0}$) in the spectrum domain is no more a discrete (impulse nature) spectral line, it gets extent over frequencies both higher and lower of the fundamental carrier (${f_0}$) in form of modulation sidebands due to random phase fluctuations or “phase noise” of the signal. The modulation process “aliased” the noise of the contaminated carrier on each of the sideband lines in the pulsed carrier spectrum. In pulsed signal, complex noise at the fundamental carrier (${f_0}$) is increased by the sum of the aliased noise on sideband lines weighted by the sampling function [sinc (x) = sin(x)/x] as shown in Fig. 1. Phase noise information at particular offsets above pulse repetition frequency (PRF)/2 gets aliased within ±PRF/2 from the fundamental carrier (${f_0}$) in the resultant pulsed carrier spectrum.

Figure 1.

Phase noise variation of CW and pulsed signal.

Any piezoelectric material-based reference crystal or dielectric substrate-based geometries becomes sensitive to the external disturbance. Basic reference crystal (piezoelectric material) acts as base clock for phase frequency detector in PLL. Hence, any phase noise performance degradation in the clock has direct impact on PLL generated signal. In addition, PLL signal phase noise is dependent on the loop filter design. Filter topology selection and order of loop filter plays important role in noise behavior. Any kind of external vibrational or accelerated disturbance initiates lattice disturbance in piezoelectric materials that gets translated in phase fluctuations. In piezoelectric or dielectric material, response to RVs is characterized by its acceleration sensitivity (normalized frequency change per unit g) and frequency drift (Δf) occurrence. Therefore, stabilization of reference clock or DR under strong vibrational environment is important for holding oscillator phase noise characteristics. In general, the effect is more prominently observed in RF frequency oscillator due to amplified phase sensitivity due to mechanical disturbances and reduced quality factor (Q) of DR. Any phase fluctuations occurring inside the oscillator feedback loop converted in frequency fluctuations via Leeson effect within the resonator’s half bandwidth. The frequency drift over the time is directly proportional to the magnitude and directional axis of applied disturbance as shown in Fig. 2 [15]. Acceleration sensitivity of reference crystal or dielectric material is measured in ppb/g.

Figure 2.

Typical axial sensitivity characteristics of piezoelectric material.

Phase noise in quartz material-based frequency source

In oscillator design, minimum one component in closed loop must offer power amplification. Piezoelectric material-based sine wave oscillator provides good frequency stability in middle of audio frequencies to throughout radio range. PLL is a negative feedback automatic control system, which can make the output signal automatically to track the changes in the reference signal. The feature enables PLL to be used as a frequency synthesizer. In a reference crystal-based frequency source design, PLL is used to control output of the VCO responsible for generation of programmed frequency. This slave oscillator output phase characteristic can be controlled within the loop bandwidth of the PLL filter. RF sensor application used in highly sophisticated airborne platform operates in X and Ku bands. Direct generation of operation frequency signal in these bands is difficult using PLL technique due to high sensitivity of the VCO. However, at the same time, it is important to miniaturize form factor and reduce switching time. PLL-based indirect technique is useful for generation of high frequency signal using multiplier along with low band PLL. In present work, X-band frequency signal is generated using S-band PLL along with frequency multiplier approach [Reference Kumar, Sivakumar, Jayasheela, Sarkar and Singh16]. S-band PLL uses 100 MHz piezoelectric material reference clock for synchronization and CP discriminator. Basic block diagram of indirect X-band PLL technique employed by multiplying S-band signal is shown in Fig. 3. The working of the frequency source is as follows: the 100 MHz reference signal passes through the power splitter, one of the output signal can be used as the system synchronization signal, the other as the reference input signal of the phase discriminator. The output voltage signal of the CP in the phase discriminator passes through the loop filter. Second order passive loop filter is chosen in designing passive loop filter, provides low resistance and high capacitance value near the VCO and offers better spurious (unwanted noise) removal feature. The VCO output frequency signal is divided into two parts through the power splitter. One path is used for final output signal after power amplification, and the other path is used as the pre-frequency division signal through the divider.

Figure 3.

Basic block diagram of PLL-based X-band frequency source.

Higher order loop filters with sharp resonance are most effective in reducing spurious leads to the enhancement in signal phase noise. Loop filter having sharp cutoff or low bandwidth is upright at the expense of higher lock time. Active PLL approach is preferred choice if CP generated is not sufficient to drive VCO in passive PLL. However, active filter results disadvantage of added in-band phase noise offered by op-amp in use. In design of low phase noise source, it is good to have at least $3{\text{rd}}$ order loop filter with extra pole helps in reduction of additional flicker noise of amplifier. Simulated phase noise performance of S-band PLL output is shown in Fig. 4. Use of multiplier for translating low frequency PLL output signal to high frequency aids in lowering phase noise filth compared to direct generation method. Phase noise variation in the derived multiplier output signal has the direct dependence on the signal phase noise prior to multiplication operation and on the multiplication ratio.

Figure 4.

S-band PLL generated low phase noise spectral signal.

Frequency source module under consideration is capable of generating frequencies with fractional bandwidth of 10 MHz. A prototype board is fabricated on substrate of RO4350B and it is mounted in aluminum enclosure as shown in Fig. 5. Printed circuit board (PBC)is composed of glass fiber-reinforced hydrocarbon/ceramic substrate (non- Polytetrafluoroethylene(PTFE), with low loss, low tolerance, and excellent high frequency performance. The air cavity of 55 mm × 55 mm × 15 mm³ is designed for avoiding radiation losses. Frequency source module finds application for airborne platform which experiences high injtensity RVs varying from range of 1 to 20 g rms. Hence, its functional check is essential under vibration stress screening to authenticate qualification of designed frequency source. RV test which is characterized by power spectral density (PSD) profile is subjected to module under test using mechanical shaker. Phase noise performance of the designed frequency source in ambient environment is shown in Fig. 6 at multiple frequency-offset points, i.e., 100 Hz, 1 kHz, 10 kHz, and 1 MHz. Phase noise is completely stable under ambient condition within the loop filter bandwidth. Kosinski states that finite element analysis method based tool finds use in industry for simulating real time environment [Reference Kosinski and Ballato17]. In RV test, PSD excitation disturbance spectrum ranging from 20 Hz to 2 kHz with amplitude level of 7.6 g rms is shown in Fig. 7. In response signal phase noise level shift $L\left( {{f_v}} \right)$ at particular offset from fundamental carrier ${f_0}$ is mentioned in equation (1) in response to the excitation [15]:

(1)\begin{equation}L\left( {{f_v}} \right) = {\text{ }}20 \times {\text{log }}(\frac{{\bar \Gamma {A_{peak}}\,{f_0}}}{{2{f_v}}})\;{\text{dB}}\end{equation}

Figure 5.

Piezoelectric material-based PLL frequency source with stabilization mechanism.

Figure 6.

Ambient condition low phase noise characteristics of piezoelectric material-based PLL frequency source.

Figure 7.

PSD spectrum ranging from 20 to 2000 Hz for random vibration test.

Here, peak g-sensitivity is ${A_{{\text{peak}}}} = \sqrt {2 \times {\text{PSD}}} $

where $\bar \Gamma $ is defined as acceleration sensitivity, ${f_o}$ is the fundamental reference clock, and ${f_v}$ is the frequency offset from ${f_0}$. $\bar \Gamma $ of reference crystal depends on PSD spectrum as depicted from equation (2) [15]:

(2)\begin{equation}\bar \Gamma = \frac{{2.{f_v}}}{{{A_{peak}}.{f_0}}}{10^{\frac{{L\left( {{f_v}} \right)}}{{20}}}}\,Hz/g\end{equation}

In the designed frequency source, 100 MHz reference clock signal acting as fundamental tone (${f_0}$) and frequency offsets ${f_v}$ are defined at 1 kHz, 10 kHz, and 1 MHz away from 100 MHz. During initial design stage, piezoelectric material with low acceleration sensitivity $\Gamma $ ($0.25\frac{{{\text{ppb}}}}{{{\text{Hz}}}}$) is selected and the design is tested at RV PSD of 0.04 $\,\frac{{{g^2}}}{{Hz}}$ which represents 7.6 g rms on the frequency source. Such high g-value RVs affects the spectral purity of a piezoelectric material based reference clock for airborne platform. To counter this, designed module is kept isolated from rest of the system using silicon rubber (acting as damper). Mounting of vibrational sensitive piezoelectric material at center of gravity of module is critical for making structure less prone to disturbance. Any phase instability occurrence in reference clock gets directly translates to final X-band PLL output signal.

Phase noise performance degradation during 7.6 g RV test at multiple frequency offsets of 100 Hz, 1 kHz, 10 kHz, and 1 MHz in the PLL generated signal has been captured and shown in Fig. 8. Trace 1 is measured phase noise of basic reference signal under ambient condition. Trace 2 is measured phase noise during RV test for basic reference 100 MHz signal. Trace 3 is measured phase noise of Intermediate Frequency (IF)signal during RV test to confirm nature of degradation. Trace 4 is the measured phase noise of final derived X-band signal under ambient condition. Trace 5 is measured phase noise during RV test for final derived X-band signal. At last measurement results are summarized in Table 1 for low phase noise frequency source with stabilization techniques for airborne platforms.

Figure 8.

During RV test phase noise of low phase noise X-band PLL source.

Table 1.

Phase noise degradation of PLL-based frequency source during RV test

Phase noise analysis of dielectric material-based frequency source

A cylindrical DR is used in the present design. Most commonly used TE₀₁ mode is excited in the cylindrical resonator, because it offers the lowest-order mode of resonance. So operating in this mode avoids the chances of the oscillator operating at resonant frequency. Three important characteristics of high frequency DR that have to be determined are: (1) resonant frequency, (2) coupling factor, (3) unloaded (${Q_u}$) and loaded (${Q_l}$) quality factors. DROs compared with other conventional oscillators such as microstrip oscillators, multiplied crystal oscillators, and cavity oscillators have advantages of small size, lower cost, ease of integration, etc. High Q DR presents excellent phase noise and temperature stability. Puck is a high Q (low loss) resonator having high value resistance with ultra-low phase noise of the resultant oscillator. At resonance frequency (${f_0}$), the DR simply acts as high value resistor R. The correct dielectric material selection has to be made taking into consideration the size and Q factor as per necessities. Full microwave spectrum ranges from 1.5 up to 40 GHz is covered through diverse materials. In DR-based oscillator design stability is enhanced with the use of high quality factor (Q) value tuning network. Dielectric cavity resonator has an unloaded Q as high as some thousands is compact and easily integrated with planar circuitry. It can be made from ceramic materials that have exceptional temperature stability. For realization of stabilized oscillator, DR geometry is placed on main substrate or adjacent substrate. It necessitates careful post-fabrication care. Various aspects of DRs are investigated and reported including magnetic coupling [Reference Guillon, Byzery and Chaubet18]. Two topology of DR coupling is shown in Fig. 9 in the form of series and parallel feedback mechanism.

Figure 9.

(a) Parallel and (b) series feedback topologies for DR coupling.

Ultra-high placement accuracy is required in the DRO assembly especially at RF frequencies. The magnetic field of the microstrip line excitation couples energy to the resonator; the tightness of the coupling is determined by the spacing (d) between the puck and microstrip line. Detailed geometric dimensions of the DR and microstrip line is shown in Fig. 10.

Figure 10.

Coupling distance (d) and magnetic coupling from microstrip line to DR.

The magnetic fringing field coupling of a DR from and to microstrip lines at 7.3 GHz is simulated using CST in order to find the DR resonant frequency (${f_0}$). Electrical spacing of the DR was determined such that the reactance at the input (base or gate) of the amplifier is the negative of ${Z_a}$. A prototype model of DRO is fabricated with DR puck diameter of 6.69 mm calculated based on Table 2, thickness of 6.42 mm, having dielectric constant of 29.5, and unloaded quality factor (${Q_u}$) of 15,000 which is placed on RT/Duroid 6010.2LM substrate of height 0.635 mm. The whole design is mounted inside a metallic enclosure. Simulation model of DR mounted on PCB substrate with microstrip lines in close proximity inside resonant enclosure cavity is shown in Fig. 11.

Figure 11.

Simulation of DR coupling on base substrate resonant enclosure cavity.

Table 2.

DR diameter and resonant frequency relation

The DR geometry is closely positioned to a 50 Ω coupling microstrip line which is terminated with a 50-Ω thin film resistor to avoid spurious oscillation. The magnetic field coupling between the DR and the microstrip line is exhibited as a parallel RLC circuit. In electrical modelling, d is the lateral distance between the DR and the microstrip line; R, L, and C are the parallel circuit resistance, inductance, and capacitance of equivalence respectively. The amount of the EM field coupling is defined as the coupling coefficient (β), which can be adjusted by changing the d value. R, L, and C values can be inferred from the equations (3) and (4) with the known unloaded factor ${Q_u}$, the coupling coefficient β, and the resonant frequency ${f_0}$ as mentioned in papers [Reference Lee, Ryu and Yom19–Reference Rogers22]:

(3)\begin{align} {\omega _0} & = 2\Pi {f_0} \nonumber \\ R = 2{Z_0}\beta &= 2 \times 50\beta = 100\beta \end{align}

(4)\begin{equation}{\text{L}} = \frac{{\text{R}}}{{{{{\omega }}_0}{{\text{Q}}_{\text{u}}}}},{\text{ C}} = \frac{{{{\text{Q}}_{\text{u}}}}}{{{{{\omega }}_0}{\text{R}}}}\end{equation}

Figure 12 shows the S-parameter of the microstrip lines with and without DR placement. A 30 dB relative coupling gain (S ₂₁) is achieved during simulation between two microstrip lines through magnetic field coupling and DR self-resonance as shown in Fig. 12(a) and (b). Return loss of −11 dB is achieved at 7.6 GHz resonance. The coupling coefficient β and loaded quality factor ${Q_l}$ can be derived from equations (5) and (6):

(5)\begin{equation}{{\beta }} = \frac{{{\text{mod }}{{\text{S}}_{21}}}}{{2.{ }\left( {1 - {\text{mod }}{{\text{S}}_{21}}} \right)}}\end{equation}

(6)\begin{equation}{Q_{\text{l}}} = \frac{{{f_0}}}{{{{\Delta }}f}}.\end{equation}

Figure 12.

S-parameter simulation of the microstrip lines and DR.

In the design process, DR resonant frequency ${f_0}$ is maintained and simulated slightly lower than the actual DRO frequency depending on the height of the aluminum cavity that has impact on DR resonance as shown in Fig. 13. The distance between DR and microstrip lines along with metallic enclosure top plays crucial role in DRO design. In this work, simulation analysis is divided into two parts: first, carrying out the EM field emulation in CST software. In CST coupling model of microstrip and DR has been simulated. After that of two-port S-parameters of the model are extracted in S2P file for the further circuit simulation. In next stage, complete low noise frequency circuit simulation is carried out in ADS. It was ensured that DRO must hold on the start-up condition and obtain a higher power and lower phase noise performance [Reference Lee, Ryu and Yom19]. Bipolar Junction Transistor(BJT)offers best noise characteristics in amplifier design that makes it suitable for the frequencies less than 10 GHz. The noise characteristics of the Field Effect Transistor(FET) is inferior to those of the BJT is not preferred choice for low phase noise. In order to obtain a low phase noise DRO, first step is selection of active device with low noise performance. Active device selected should have high cut-off frequency, low noise figure, and sufficient loop gain. However, normally all these conditions cannot be satisfied all together and it needs weighted trade-off.

Figure 13.

Illustration of DRO enclosure height, placement position, and coupling distance (d).

Minimizing phase noise and jitter

In target with design of low phase noise DRO, critical design consideration for frequency resonator are: (1) maximize the Q-factor of the resonator network, (2) maximize the power in resonator necessities a high RF voltage across resonator network, (3) use of low noise figure active component, (4) minimum flicker noise, and (5) ensuring maximum energy coupling from the resonator rather than another point of the active device [Reference Kumar, Sivakumar, Jayasheela, Sarkar and Singh16]. Transistor bias configuration Common Emitter(CE) and Common Base(CB) is selected for design and accordingly phase shift of the transistor compensated to align with the input signal phase. DC biasing circuit is made to bias the BJT transistor at the accurate operating point to ensure oscillations. The bias point is set at ${V_{ce}}$ = 5 V and ${I_c}$ = 22.7 mA with passive bias circuit. Matching network has been designed with single stub line circuit. Radial stub is used for this bias circuit to provide a short resonant circuit. The stub converts the open circuit at the surface edge of the radial part to a short circuit at narrow width (high impedance) microstrip line. Then same short circuit is converter to an open circuit at a quarter wave length ($\frac{\lambda }{4}$) along the microstrip line. The input impedance of the active part side, X (l) is used to calculate the length (l) of the microstrip line which defines the position of the DR [Reference Guillon, Byzery and Chaubet18]. The impedance matching circuit is designed using ADS software. The matching circuit is fulfilled in such a way that the reflection, looking back at the input and output should be more than unity, i.e., ${S_{11}}$, ${S_{22}} \gt 1$. Maximum power transfer between the source (${Z_s}$) and the load (${Z_l}$) is achieved with sustainable oscillating condition. Model representation of DR coupling resonator and single stub matching network is shown in Fig. 14.

Figure 14.

DR coupling resonator and stub matching network.

During the design process of low phase noise DRO, both linear and nonlinear analysis of the stable frequency source has been executed. Linear analysis is based on small-signal model only considering terminal S-parameters. It only promises that the designed DRO would produce oscillations and the approximate value of resonant frequency. While the nonlinear analysis is based on true large signal conditions (more realistic). Schematic design circuit of low phase noise DRO implemented in ADS software is shown in Fig. 15. BJT is replaced by its nonlinear model, and the bias point is set at ${V_{ce}}$ = 5 V and ${I_c}$ = 22.7 mA. In schematic design, oscillator test in linear analysis is alternated with oscillator port in nonlinear model. The electrical length (l) of the open stub line is optimized to $52^\circ $, to ensure the magnitudes of ${S_{11}}$ and ${S_{22}}$ being at least 1.2 to generate acceptable negative resistance and the locus being symmetrically centered on the oscillating frequency (${f_0}$). In line with negative resistance theory, the DR-based low phase noise frequency source is designed to make the resistance generated by the feedback element negative enough to compensate the loss generated by the resonator [Reference Kajfez and Guillon23, Reference Banerjee24].

Figure 15.

ADS design circuit schematic of low phase noise DR-based frequency source.

In nonlinear model analysis, the R, L, C values of the of the resonator equivalent circuit are set to vary upon the known coupling coefficient β, oscillating frequency ${f_0}$, and unloaded Q-factor ${Q_u}$. Consequently, the placement of the DR geometry can be optimized by fine-tuning the value of β in the nonlinear analysis when ${Q_u}$ and ${f_0}$ have already decided. Important aspect in design according to Leeson’s model, the loaded Q-factor ${Q_l}$ is one of the main reasons resulting in phase noise. To achieve low phase noise, ${Q_l}$ is optimized in the design phase. Collectively, ${Q_l}$ is affected from active device material and its operating bias conditions, supporting passive circuitry, ${Q_u}$ of the resonator geometry and EM field coupling parameters.

All the interrelated parameters in nonlinear analysis are fine-tuned in order to achieve low phase noise while maintaining sufficient output power and frequency stability. PCB layout design of low phase noise DRO as per ADS design schematic is carried out for common emitter configuration to yield low phase noise characteristics of output signal as shown in Fig. 16. Power supply design is carried out with having ultra-low noise regulator with capacitive filtering at input and output. The simulation results for linear and nonlinear analysis show that the frequency source would oscillate around 7.6 GHz as shown in Fig. 17 [Reference Kosinski and Ballato17, Reference Wallin, Josefsson and Lofter25–Reference Hajimiri and Lee27]. With the combination of feedback element, controlled magnetic field coupling and matching network, the constant power transfer between the source and the load has been achieved with oscillations.

Figure 16.

DRO parallel feedback common emitter configuration.

Figure 17.

Harmonic performance simulation of low noise DRO.

Figure 17 shows simulated harmonic performance of the oscillator. One of the important characteristics of a designed frequency source is the phase noise at 10 kHz or further away from the carrier. Simulated phase noise characteristics over the frequency offsets as per design and fine tuning mechanism has been shown in Fig. 18. In this case, the phase noise measured as −126 dBc/Hz at 100 kHz of frequency offset. Table 3 describes comparison with other similar type of works reported earlier.

Figure 18.

Phase noise performance simulation of low noise DRO.

Table 3.

DRO phase noise comparison with other previous works

Note:

NM – not mentioned.

After executing the circuit simulation, a highly skilled assembly testing and optimization work is necessary to realize the design practically. In the process of optimization, DR puck is tuned in horizontal and vertical axis to find the best placement between microstrip lines until the best figures of low phase noise and good output power. Spectral impurity occurrence from other frequencies apart from 7.6 GHz resonance has been filtered out by the placement of narrow band isolator before final output signal. During assembly process, passive components are mounted first and then active devices are mounted. With the success in simulation, a prototype board is housed in aluminum mechanical housing. The air cavity of 55 mm × 55 mm × 15 mm is designed for the purpose of avoiding radiation losses. PCB is fabricated using substrate of 0.635 mm height RT/Duroid 6010.2LM. DR is attached to PCB for getting 13 dBm output power at 7.6 GHz with second-order harmonic of −20 dBc. Ambient condition phase noise performance of realized low phase noise DR-based frequency source has been captured and shown in Trace A of Fig. 19 at different offset frequency points, i.e., 1 kHz, 10 kHz, and 1 MHz.

Figure 19.

Ambient and under random vibration condition results of phase noise in low noise DRO.

RV conditions have been emulated for verification of module performance due to dielectric material disturbance under intense vibrational environment for the use in airborne platform applications. Trace B of Fig. 19 represents phase noise of the developed DR source. Three axes responses under RV test are summarized in Table 4. Precise observations and analysis for DR response helped in understanding impact of unintentional coupling of vibrations on sensitive components of piezoelectric or dielectric based design. During design phase analysis of acceleration sensitivity and its impact helped in execution of stabilization and compensation [Reference Kosinski and Ballato17, Reference Kajfez and Guillon23, Reference Banerjee24]. Table 1 reports that phase noise performance during RV test significantly degrades in comparison to ambient condition at an offsets of 1 kHz and its value is around ∼37 dB. In spite of that Table 4 reports phase noise performance degradation in comparison to ambient condition at an offsets of 1 kHz and the value is around ∼15 dB.

Table 4.

Phase noise variation of DR-based signal source during random vibration test