II. ANALYSIS AND DESIGN OF THE POWER DIVIDER

Figure 1 shows the circuit layout of the conventional Bagley Polygon power divider, which is composed of two λ/2 length TLs and two λ/4 length TLs. Based on the theory in [Reference Sakagami, Wuren, Fujii and Tahara25], $Z_a = 2Z_0/\sqrt 3 $ , while Z _b is arbitrary. The output of the power divider is equal in amplitude. The phase of port 2 and port 3 is same and out-of-phase with port 4. The power divider shows 10-dB isolation performance between the three output ports [Reference Oraizi and Ayati23]. In this paper, the two λ/2 length TLs are replaced by 0° TLs.

Fig. 1.

The circuit of conventional Bagley Polygon power divider.

The 0° phase shift TL is realized by the CRLH and conventional microstrip TL. The CRLH TL provides the positive phase shift, and the latter provides the negative phase shift. Figure 2(a) shows the structure of the CRLH part. Figure 2(b) is the equivalent circuit of the CRLH TL. Interdigital capacitor provides the left-handed capacitor C _L . The short-ended stubs provide the left-handed inductors L _L . Based on the theory in [Reference Ren, Song, Fan, Zhu and Hu22], the phase response of the CRLH TL can be calculated by equation (1):

(1) $$\eqalign{\varphi & = \pm n \times \arccos [ {1 - ({\omega ^2L_RC_R + 1/\omega ^2C_LL_L} )} \cr & \quad + {({C_R/C_L + L_R/L_L})}],}$$

where the “±” sign denotes that the phase shift is negative in the left-handed band and positive in the right-handed band, n is the number of the CRLH cells; ω is the angular frequency. In order to apply this structure into the circuit, the impedance must be equal to Z _b . The impedance of the CRLH TL can be calculated by equation (2):

(2) $$Z_B = \displaystyle{{ \pm \left( {j\omega L_R + {1 / {j\omega C_L}}} \right)} \over {\sqrt {{\left[ {1 + \left( {{1 / {j\omega L_L}} + j\omega C_R} \right)\left( {{1 / {j\omega C_L}} + j\omega L_R} \right)} \right]}^2 - 1}}}, $$

where Z _B indicates the Bloch impedance. Based on the CRLH TL theory, the balance condition is

(3) $$L_RC_L = L_LC_R = {1 / {\omega _0^2}}, $$

where the ω ₀ is the center angular frequency. Based on the balance condition, the equation (2) can be simplified to

(4) $$\sqrt {{{L_L} / {C_L}}} = \sqrt {{{L_R} / {C_R}}} = Z_B.$$

Fig. 2.

(a) The structure of the CRLH TL. (b) Equivalent circuit of the CRLH TL.

The Z _B should be equal to Z _b . In reality, the phase response of the CRLH TL (φ) should be set bigger than 0. The CRLH structure should connect with other part of the power divider through the microstrip TL, which will introduce some negative phase shift. The structures of the miniaturized Bagley Polygon power divider and the 0° TL are shown in Fig. 3. The dimensions of CRLH TL in Fig. 3 are as same as in Fig. 2.

Fig. 3.

Circuit layout of the miniaturized Bagley Polygon power divider.

If the φ and C _L are given, the parameters C _R , L _L , and L _R can be calculated based on the equations (1), (3), and (4). The other part of the power divider is same as the conventional type as shown in Fig. 1. The C _L can be implemented based on the empirical equation [Reference Caloz and Itoh28]:

(5) $$C_L \approx (\varepsilon _r + 1)l\left[ {\left( {N - 3} \right)A_1 + A_2} \right].$$

Here,

(6) $$A_1 = 4.409\;\tanh \left[ {0.55{\left( {\displaystyle{h \over {\omega _f}}} \right)}^{0.45}} \right](pF/\mu {\rm m})$$

(7) $$A_2 = 9.92\;\tanh \left[ {0.52{\left( {\displaystyle{h \over {\omega _f}}} \right)}^{05}} \right](pF/\mu {\rm m}),$$

where, ε _r is the dielectric constant of the substrate; l, N, and ω _f denote the length (l _f ), number, and width of the interdigital line, respectively; h is the height of the substrate.

III. EXPERIMENT AND RESULTS

For experimental demonstration, the proposed miniaturized Bagley Polygon power divider is designed and fabricated on substrate Taconic RF-35 with dielectric constant of 3.5, thickness of 0.508 mm, and loss tangent of 0.0018. The center frequency is 3.5 GHz. According to above design procedure, the initial dimensions of the proposed power divider can be obtained firstly. Then the HFSS (high frequency structural simulator, a commercial finite element method solver for electromagnetic structures from Ansys) is utilized to simulate and optimize. After optimization, the final sizes of the power divider are: L ₁ = 16.9 mm, L ₂ = 4 mm, L ₃ = 3.4 mm, W ₁ = 0.87 mm, W ₂ = 0.6 mm, l _s  = 5.4 mm, w _s  = 0.2 mm, g = 0.15 mm, S = 0.15 mm, l _f  = 4 mm, w _f  = 0.2 mm, D = 0.5 mm. The λ/4 sections are bended to further reduce the total size. The fabricated Bagley Polygon power divider is shown in Fig. 4.

Fig. 4.

Photograph of the fabricated Bagley Polygon power divider.

The simulated and measured results of the fabricated Bagley Polygon power divider are shown in Fig. 5. It can be seen that the measured results show a reasonable agreement with the simulated ones. The input return loss is >15 dB in the center frequency. The maximum insertion loss between the three output ports is 4.89 dB (4.77 + 0.12 dB). Figure 5(a) shows the good amplitude imbalance at the center frequency. Figure 5(b) shows that the S ₂₃, S ₂₄, and S ₃₄ are 10.12, 9.27, and 10.14 dB, respectively, which demonstrates that the miniaturization does not deteriorate the isolation performance of this type of power divider. In this design, the 0° phase shift TL is utilized to replace the 180° TL. Based on the TL theory, the output ports should be in-phase instead of out-of-phase. Figure 6 demonstrates the success of the design method, although there is some imbalance between the three output ports. As for imbalance at 3.5 GHz between the fourth and the other output ports, some measurement error may cause it and make the in-phase frequency deviate from the 3.5 GHz. To the point, it has no effect on the performance of the power divider.

Fig. 5.

Simulated and measured results of the fabricated power divider. (a) Insertion loss and return loss; (b) isolation.

Fig. 6.

Measured phase response of the miniaturized Bagley Polygon power divider.

In addition, the number of the output ports can be added by simply inserting the 0° phase shift TL between the two arbitrarily adjacent output ports without other calculation or extra analysis. It also avoids the limitation of the realizable impedance during the fabrication. Table 1 compares the performance of the proposed design and other miniaturized Bagley Polygon power dividers reported in recent years. It demonstrates that the proposed power divider has realized the significant size reduction and maintained its isolation performance. Although the size of the proposed power divider is larger than that in [Reference Li, Liu, Li, Yu and Wu27], our work features easier assembly and isolation maintained.

Table 1.

Comparison with some prior miniaturized Bagley polygon power divider.

* The ratio of the size of proposed power divider and the size of the conventional Bagley Polygon PD (λg/2*λ _g/4); IL, insertion loss.